[PCB_FORUM] Constraint Enabled ERROR

#1   ERROR(300) Net Rev fatal error detected.

Design flow is Constraint Manager enabled, require pstcmdb.dat and 
pstcmbc.dat files.

 This is from a board that was done a year ago using Allegro and Concept 
HDL 15.5 Without ANY constraints added to either the board or the 
schematic. We now have 15.7 loaded and want to do an ECO to the layout, 
the Eng. makes the schematic change and when we run the loop from Project 
Manager ( Export Physical ) it packages clean but we get the error above 
while tying to update the board file. I don't want this project CM 
enabled, I don't have anything to enable! I guess I'll have to be CM 
enabled but how do I get the 2 files above that I need? 
 The question is this:   Why are we constraint enabled we don't even have 
a lic. for ConceptHDL that can open CM? We are not doing anything 
different ( maybe we should be ) from the way we've been doing ECO's for 
years. Are we the only people having this trouble since we upgraded to 
15.7, also we do have many boards that are using CM for much of the 
placement and routing ( I really like it ) but every simple schematic 
change like adding a resistor we have trouble with the CM enabled problem

   Thanks


Paul Keefe ( Dumbass )

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