[PCB_FORUM] Re: Changing netnames in Allegro not back-annotated to ConceptHDL schematics...

Well, I don't envy you your position.
Sometimes you have to cheat to get the tool to do
what you want. Especially in the type of scenario
you have. That said, the tool just won't allow
you to change the net names without working around
the normal flow. (As suggested in another reply.)
One of the nice (in my opinion) things about the
cadence tools is so much stuff exists in ascii
files you can go and modify as you like. This can
break stuff for sure, but does give you a lot
of power to "subvert" the system.

Kevin

Austin Franklin wrote: 
Hi Kevin,


Sounds like a good idea to me.
To not be able to do that, I mean.



Well, I disagree, and obviously believe that you should be able to change
things in the design file and back annotate them.  It's not my preferred
design methodology, but there are instances when it makes perfect sense to
be able to do this, instead of forcing a square peg into a round hole.


Why would you want to do that from Allegro, anyway? 


Not that it should matter, as I believe this is a basic function back
annotation function (or why have back annotation)...but we have a design
that originated in Viewdraw, per the customer's requirements...then the PCB
was done in Allegro.  Subsequently, they changed their requirements and need
ConceptHDL schematics.  We drew them, and they match perfectly, except for
the default names assigned to signals that aren't intentionally named.  If
we could back annotate the .brd file names to the ConceptHDL schematics,
then they would match perfectly.


Doesn't the schematic drive the design in your group? 


Yes, as much as can be, and personally, I would prefer it be done that way.
But, sometimes the tools don't allow it to be done easily.  For example,
Allegro Performance has the constraints manager in it, which allows easy
specification of constraints...but the ConceptHDL that comes with any of the
200 series tools does not have the constraints manager.  You have to add
constraints to the schematic through a rather tedious process (though the
base level Viewdraw has a constraints manager...chalk one up for Viewdraw
over Concept).  So constraints are easier to add in Allegro with it's
constraint manager, than directly on the schematic, and then simply back
annotate them to the schematic.

I was rather perturbed that our rather expensive (though not the most
expensive) tools (schematic and layout) weren't "compatible" as far as
capabilities, and we aren't going to spend another $40k to simply get a
constraints manager in the schematic tool.

Regards,

Austin


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