[PCB_FORUM] Can I tie a Port Symbol to a net with a symbol tied HDL_POWER attribute?
- From: FranciscoMontoya@xxxxxxxxxxxxxxx
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 26 Jul 2007 16:51:25 +0800
Hello,
When we started creating hierachical designs, we're having difficulty
connecting a port symbol to a wire tied to another symbol with a HDL_POWER
attribute embedded. If we pushed it, we either encounter packing problems
or failed cref run.
Is there a way I can have both? I've first seen this during v15.
thanks,
bambam
J. Francisco D. Montoya
Group Supervisor
PCB Design Group
Astec International Limited
4/F Technoplaza One
18 Orchard Road, Eastwood City
Libis, Quezon City
Philippines 1110
Phone: (632) 995-4000 loc 4438
Email: franciscomontoya@xxxxxxxxxxxxxxx
Other related posts:
- » [PCB_FORUM] Can I tie a Port Symbol to a net with a symbol tied HDL_POWER attribute?