[PCB_FORUM] Cadence Designer

Well known semiconductor manufacturing company has an opening for a full
time Printed Circuit Board Layout Designer in Phoenix, AZ facility. This
person will be part of a global layout Team responsible for layout of
production ATE test boards for Final Test and Probe.

This candidate will manage the assigned design project working with internal
Engineering customers and also with worldwide New Product Introduction
groups to complete the design project per plan.  Day to day duties include
schematic capture, parts placement, Rules setup, and pcb layout tasks
including creation of library parts.

The ideal candidate will have an AA degree and over 3 years of experience in
layout for ATE production boards testing. Candidate must be experienced in
Cadence Allegro and Design Entry CIS (OrCAD ) for PCB schematic capture,
layout and library parts creation and support. Hands on experience must
include  Digital,  Analog, and  RF board design.  Additional skills in
Design Rules Checkers, and simulation tools are preferred.

If you have any questions or would like to submit a resume, please contact
the address below.

Jim B.

Design Layout Manager
Jimba100@xxxxxxxxxxx

-----------------------------------------------------------
To subscribe/unsubscribe: 
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
with a subject of subscribe or unsubscribe

To view the archives of this list go to 
http://www.freelists.org/archives/icu-pcb-forum/

Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
-----------------------------------------------------------

Other related posts: