[PCB_FORUM] Re: CDNLive! Conference
- From: "Todd Westerhoff (twesterh)" <twesterh@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 7 Jul 2005 17:46:31 -0400
Carl,
Having abstracts on-line will certainly help everyone judge whether they
can expect to learn things that are relevent to their current work. I
can't speak for you or your work; only you can.
Traveling 3000 miles for a day's conference is hard on the body, if not
the budget. It sounds as though you might find it useful to attend both
Monday and Tuesday, including the vendor fair and technology night.
An observation - airfare has become so cheap it's no longer the dominant
cost in many of my trips. My last airfare to CA was $450, which
included flying into LA and out of San Jose. My hotel costs exceeded
the airfare, my rental car almost did. My point - traveling to the West
Coast for two days is not necessarily cost prohibitive, if you get a
good airfare.
However, that's up to you.
Feel free to contact me at the address below if you'd like to discuss
this further.
Todd.
Todd Westerhoff
High Speed Design Group Manager
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"Always do right.
This will gratify some people and astonish the rest."
- Mark Twain
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]
Sent: Thursday, July 07, 2005 4:27 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: CDNLive! Conference
Todd,
I completely agree with you assessment on the way that system
design is being affected by the signal speeds and the die packaging has
caused me a lot of pain in some of my recent designs. As a matter of
fact the more I think about there are some tool gaps that seriously need
to be addressed by Cadence. How can I set a diff pair phase tolerance at
20 mils in allegro when the pair is routed out the die package with the
tolerance greater than 20. Zero doesn't even work here! I have
experienced similar issues with the rel prop delay. Maybe I am missing
something and do need to get some better high speed tutorials because
the way I have been solving the problem is with an excel spread sheet
and formulas. I believe one thing that would help would be to have a net
property with cline length from the die package and of course I would
want the data auto loaded from Allegro/APD. But back to the APD papers
on Monday am I to get out of this that if I go to the conference on
Monday and a ttend these papers I will be better able to deal with
these issues in PCB the design arena with allegro? Put more bluntly will
my boss notice an improvement in turnaround time and quality of design
by attending? For me and probably many others this is the crux of the
biscuit.
I believe, will be able to make a better judgment upon reading
abstracts, the Tuesday Allegro and capture material is adequate and
worth seeing. The Wednesday session revolves around high speed design
and yes I would be interested but we don't use Spectra quest and
probably will not until core tool issues with high speed design such as
the one mentioned above have been resolved. So I am on the east coast
why would I go 3000 miles for one day?
Carl
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