[PCB_FORUM] Re: Allegro to DxDesigner (back-annotation)
- From: "richard moffat" <richard.moffat@xxxxxxxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Tue, 08 Nov 2005 10:27:33 +1300
Thanks Jerry
I'm making the following assumptions:
- the abk is generated from Allegro's 'Net List Report'
- the tl2 is generated from Allegro's 'Netin (back annon.)'
Of course, these assumptions aren't based on anything concrete, and it doesn't
work!
Some things in the report:
"pcb: Warning 5776: Raptor_eight_main com $2I1133: Manually delete component"
"pcb: Failure 5806: Component $60I0 not found on sheet 60 of design
raptor_eight_main."
"pcb: Error 5815: Pinname NC_2 does not exist on component mictor38r."
Problem is, there is no sheet 60; the back-ann added it. I believe the pinname
error is because of a mechanical pin.
I'm only trying to swap resistor network pins. I may quickly write something
myself just to change the netnames.
Cheers,
Richard
>>> gerry.meier@xxxxxxxxxxxxxx 8/11/2005 9:11 a.m. >>>
Richard,
I recently received these instructions. I haven't actually tried this
process yet (disclaimer)
Allegro to DxDesigner (back-annotation)
You need to find out what he has for a Project name. This will be the
name that he called his schematics.
Once you receive this you well need to send him a file with the
following names:
Export the third party logic with the name: <Project Name>.abk
Export the netlist/w properties with then name: <Project Name>.tl2
This will be for use with the Allegro 14 config file.
************* Back Annotation Switches **************
BackExt abk | Extension of Allegro's third party back annotation file.
DoAttBackan yes | [yes] | Controls whether Allegro net attributes are
| backannotated to the schematic. [yes] requires
| an Allegro backward netlist.
|BackNetlistFileName |backward netlist file and extension. Default is
<design>.tl2
BackNetFileExt tl2
SuppressIdBackAnno yes | [no] | Controls the back annotation of Allegro
IDs.
| DumpDict should be set to yes if back annotation of Allegro IDs are
not
| required.
OutPinDelay no | [no] | Controls if .dtb file will be created during
pcbbck
| from results of Allegro's tldelay program.
InPinExt ipn | extension of output of Allegro's tldelay program
OutPinExt dtb | extension of Viewlogic delay table file
|InPinFnme | Default is <design name>
|OutPinFnme | Default is <design name>
Regards,
Gerry
Gerry Meier
Sr. PCB Designer
Freedom CAD Services, Inc.
Voice: (603) 864-1300 x1350
AL Voice: (256) 417-6944
Email: gerry.meier@xxxxxxxxxxxxxx
visit our website at<http://www.freedomcad.com
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of richard moffat
Sent: Monday, November 07, 2005 1:52 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Allegro to DxDesigner (back-annotation)
Hi
I've just been looking for the back-annotation documentation. I saw
some detailed instructions a while ago, but now I can't find much at
all. (I think it was in the ViewDraw install.)
Can anyone point me to it?
Cheers,
Richard
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