[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

Hi Soledad,

>   Logic
>     -net schedule RMB insert T (this should be the midpoint of route
>  Setup Constraints
>     Relative propagation delay
>      Select net create pin pair
>         Create match group

To add to this...

Without knowing more about your application, I don't know if you care about
that there is length matching between the source and the "T", and I'll
assume not.  Setup a pinpair from source to destination 1 and source to
destination 2 for each net, and put them all in the same length match group.
You shouldn't need any pinpairs containing the T.

As a note on length matching.  A 50 mil length match with a propagation of
166ps/inch would be a length match of about 8.3ps length match.  If you were
length matching to %2 of the frequency (which is quite "tight"), that would
be a frequency of 6GHz!

Why I question the 50 mil length match, is sometimes, engineers aren't
really sure how to calculate length match tolerance, and they come up with
these really unnecessary tolerances.  It isn't really that hard to
calculate.  You just have to know the frequency, and to what percent you
need, or know what the amount of time is the design can tolerate.  What the
design can tolerate is derivable from the spec sheets of what is being
interfacing to...but %2 of the frequency is a pretty good (and tight) rule
of thumb IMO.  Calculate the length delay using 166ps/inch (typical for
FR-4) or what ever the proper prop. delay for your material is.

For example, if you are interfacing to 333MHz DDR, it's actually a rate of
666MHz (double data rate...as each edge is used), and say you want to use a
%2 tolerance.  %2 of 666MHz is 1/(.02 * 666MHz) = 75ps, and 75ps /
166ps/inch = .45 inches.  If you use a target (a clock) you can typically
use +/- 450 mils, making length matching and routing MUCH easier.

Regards,

Austin

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