[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

From: "Brian Alcock" <brian.alcock@xxxxxxxx>
To: <icu-pcb-forum@xxxxxxxxxxxxx>
Date: Wed, 27 Feb 2008 16:32:52 -0500

 

 

  Constraint manager  

          Signal FLASH_DQ16.T is midpoint (create a pin pair from this
point to your IC's

 

 

 

 

 

 

 

 

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Soledad Attia
Sent: Wednesday, February 27, 2008 4:23 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Allegro V6.01 Constraint Manager

 

Thanks so much for the help

Will try this

Regards

S. Attia

 

-----Original Message-----

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx

[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] 

Sent: Wednesday, February 27, 2008 1:12 PM

To: icu-pcb-forum@xxxxxxxxxxxxx

Subject: [PCB_FORUM] Re: Allegro V6.01 Constraint Manager

 

Soledad

  Logic

    -net schedule RMB insert T (this should be the midpoint of route

 Setup Constraints

    Relative propagation delay 

     Select net create pin pair

        Create match group 

 

 

-----Original Message-----

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx

[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Soledad Attia

Sent: Wednesday, February 27, 2008 3:58 PM

To: Soledad Attia; icu-pcb-forum@xxxxxxxxxxxxx

Subject: [PCB_FORUM] Allegro V6.01 Constraint Manager

 

Hi All,

 

 

We just recently upgraded to Allegro V6.01 and have been trying to work

with the constraint Manager to create matching lengths for a bus; but

have not been able to.

Does anyone know the sequence of steps to accomplish this? and willing

to share the information?

Appreciate any help

Thanks

S. Attia

Printronix Inc

Irvine, Ca.

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References:

[PCB_FORUM] Re: Allegro V6.01 Constraint Manager
From: Soledad Attia

[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

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