[PCB_FORUM] Re: Allegro V6.01 Constraint Manager
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 27 Feb 2008 16:11:48 -0500
Soledad
Logic
-net schedule RMB insert T (this should be the midpoint of route
Setup Constraints
Relative propagation delay
Select net create pin pair
Create match group
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Soledad Attia
Sent: Wednesday, February 27, 2008 3:58 PM
To: Soledad Attia; icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Allegro V6.01 Constraint Manager
Hi All,
We just recently upgraded to Allegro V6.01 and have been trying to work
with the constraint Manager to create matching lengths for a bus; but
have not been able to.
Does anyone know the sequence of steps to accomplish this? and willing
to share the information?
Appreciate any help
Thanks
S. Attia
Printronix Inc
Irvine, Ca.
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