[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

Again, thank you all for your help and comments and for sharing your
knowledge; really appreciate  all the information.
Regards
Soledad

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Wednesday, February 27, 2008 5:02 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Allegro V6.01 Constraint Manager

Hi Richard,

> I think you have to be careful giving advice on tolerances.  They
> are most definitely this tight in many circumstances.

I don't know about many, but certainly some.  My advice was simply
citing an
example, not giving a specific rule to follow, and how to calculate it
for
your self.  Hence why I said "If you were length matching to %2...",
note
the "IF".  The problem is, MANY engineers (and PCB designers) don't
understand what a reasonable length match is, and how to calculate it.
They
just specify some number, that has no basis in proper engineering.

> An example of this is the crossover period for differential '+'
> and '-' pairs.  A mismatch here will cause an imbalance in the
> ground return causing both SI (crosstalk in this case) and
> possibly EMC problems, not to mention problems at the receiver.

Correct, but we weren't talking differential signaling.  And, that's not
technically a length match, that's a phase tolerance, which Allegro
handles
differently than length matching.

> We typically match to less than +/- 10% of the rise time,
> although we look at each case independently.

You can have a 1MHz signal with a 500ps rise time...and no need to match
that to +/- 50ps!  Rise time is very important for other things (like
termination, and routing to eliminate anomalies in the signal), but for
figuring out length matching, though it enters into the equation,
frequency
is far more pertinent if you want to get a general feel for what might
make
sense.  At least in my experience, and so far I haven't had a design not
meet specs nor fail.

> In this case, the 'T' based memory topologies are very particular
> in matching from the t-point to each memory device.  It's not so
> much the timing you'll worry about - it's the reflections that
> don't cancel each other out.  (Again, SI and/or EMC.)

Well, matching from source to D1 and source to D2 DOES match the T to D1
and
to D2 for that net!  You *need* a match from source to every
destination,
and in specifying all source to destination pinpairs, you automatically
get
a length match from the Ts to the destinations, on a per net basis.  You
typically don't need to length match the Ts to destinations between
nets,
only within a single net.

> If the tolerances are not matched because they seen ridiculous,
> and the board doesn't work - guess what the chip manufacturer is
> going to point at?  That's right - the poor design that didn't
> follow their specs.

My point is, where do these length match numbers come from?  These
things
aren't spec'd in the datasheets, directly, typically...though some do.
If
the datasheet says length match to 100 mils, then of course, do it (even
though some datasheets are simply silly in their length match
requirements,
but I agree...you do what the manufacturer specs).  But if no, you need
a
way to understand first if you need to length match, and second how to
calculate what to length match to.  As opposed to just guessing that 50
mils
seems like it's good enough.  Overspecing something like this can make
the
PCB layout job an order of magnitude harder, and can even cause problems
elsewhere, like having excess trace that can lead to yet another set of
problems.  What you have to do is keep the eye open sufficiently to meet
the
specified setup and hold over the operating range of the parts.  And
allow
some room.

> My point is that sometimes the maths for loose tolerances may
> make sense but there are other factors that go beyond the basics.

Well, %2 of frequency isn't really a loose tolerance!  I chose %2 to
show
what frequency a 50 mil tolerance would could be used for.  It's a
ballpark.
If the signaling that was being length matched were, for example,
200MHz,
then there is reason to question the 50 mils.

> As an absolute coincidence, my colleague just informed me that
> the new datasheet for our QDR ram has halved the tolerance for
> the address to +/- 250 mils (internal layers).  I would tend to
> trust them; obviously they know something we don't.  (Yes, I know
> that address lines generally have a looser tolerance than data
> and clocks.)

+/- 250 mils is 500 mils...lots of room, and sounds about right.  Far
better
than trying to length match to 50 mils!

> Speaking of clocks, they should almost always be
> the target unless otherwise specified.

IF there is a clock.  Not all "busses" have clocks.

> I'm sure Soledad appreciates your comments, but this wasn't what
> he was asking.

I know that wasn't what he was asking, but he did say he was given a
length
match of 50 mils, and I wanted to understand why.  For the reasons I've
stated, that most people don't know what it is they are specifying,
especially when I see a spec like this.  I also asked specifically for
more
information on what he was doing...so I could make a more informed reply
to
his situation.

Regards,

Austin

-----------------------------------------------------------
To subscribe/unsubscribe: 
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
with a subject of subscribe or unsubscribe

To view the archives of this list go to
http://www.freelists.org/archives/icu-pcb-forum/

Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
-----------------------------------------------------------
-----------------------------------------------------------
To subscribe/unsubscribe: 
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
with a subject of subscribe or unsubscribe

To view the archives of this list go to 
http://www.freelists.org/archives/icu-pcb-forum/

Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
-----------------------------------------------------------

Other related posts: