[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

Hi Randy,

Thank you for the links.

<snip>

I didn't see anything in there that said there was a more critical length
match from T->D, than from S->D, or did I miss that?  I didn't read them all
word for word, and some of them I'd seen before.  I'll read them more
tomorrow when I get some time.

One note on the "plat7justin.pdf".  It only mentioned length matching for
DQS/DQ/DM, nothing about address/control except that it's "less critical".
It's useful information, but incomplete IMO.

Component DDR (as in components on the board) have different requirements
than module DDR.  Most app notes cover module DDR (such as the
plat7justin.pdf), not component DDR.  I did provide the layout requirements
on some app notes for Xilinx that were specifically for component DDR, so
there are at least those out there you can find on the Xilinx website.

Regards,

Austin

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