[PCB_FORUM] Re: Allegro V6.01 Constraint Manager




Perhaps some links and practical examples will help.

(Ohhh my look at all those Micron links, and references, I wonder how they got 
in there...)

Randy


http://download.micron.com/pdf/presentations/dram/plat7justin.pdf

http://download.micron.com/pdf/technotes/DDR/tn4614.pdf

http://www.cdnusers.org/Articles/Siliconpackageboard/tabid/118/Default.aspx?topic=Design-in%20kits&subtopic=Memory%20Interfaces

http://www.cdnusers.org/InterviewDesigninginDDR2memoriesonPCBs/tabid/401/Default.aspx

http://focus.ti.com/lit/an/spraac5f/spraac5f.pdf

Date: Thu, 28 Feb 2008 15:40:52 +1300
From: richard.moffat@xxxxxxxxxxxxxxxxxxx
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Allegro V6.01 Constraint  Manager







Looks like the italics didn't come thorough in the first post.  HTML instead:

>>> "richard moffat" <richard.moffat@xxxxxxxxxxxxxxxxxxx> 28/02/2008 3:34 p.m. 
>>> >>>

Oh, dear...  I knew this was going to happen.

I almost didn't bother replying, but comments below anyway.  (Sigh...)

>>> "Austin Franklin" <allegrolist@xxxxxxxxxxxx> 28/02/2008 2:01 p.m. >>>
Hi Richard,

> I think you have to be careful giving advice on tolerances.  They
> are most definitely this tight in many circumstances.

I don't know about many, but certainly some.  My advice was simply citing an
example, not giving a specific rule to follow, and how to calculate it for
your self.  Hence why I said "If you were length matching to %2...", note
the "IF".  The problem is, MANY engineers (and PCB designers) don't
understand what a reasonable length match is, and how to calculate it.  They
just specify some number, that has no basis in proper engineering.

> An example of this is the crossover period for differential '+'
> and '-' pairs.  A mismatch here will cause an imbalance in the
> ground return causing both SI (crosstalk in this case) and
> possibly EMC problems, not to mention problems at the receiver.

Correct, but we weren't talking differential signaling.  And, that's not
technically a length match, that's a phase tolerance, which Allegro handles
differently than length matching.

As I said, it was an example.  

> We typically match to less than +/- 10% of the rise time,
> although we look at each case independently.

You can have a 1MHz signal with a 500ps rise time...and no need to match
that to +/- 50ps!  Rise time is very important for other things (like
termination, and routing to eliminate anomalies in the signal), but for
figuring out length matching, though it enters into the equation, frequency
is far more pertinent if you want to get a general feel for what might make
sense.  At least in my experience, and so far I haven't had a design not
meet specs nor fail.

Yes there is.  It's called signal integrity and EMC.  Have a look at a couple 
of good articles by Doug Brooks sometime, as well as other resources.  

I also said we look at each case independently.


> In this case, the 'T' based memory topologies are very particular
> in matching from the t-point to each memory device.  It's not so
> much the timing you'll worry about - it's the reflections that
> don't cancel each other out.  (Again, SI and/or EMC.)

Well, matching from source to D1 and source to D2 DOES match the T to D1 and
to D2 for that net!  You *need* a match from source to every destination,
and in specifying all source to destination pinpairs, you automatically get
a length match from the Ts to the destinations, on a per net basis.  You
typically don't need to length match the Ts to destinations between nets,
only within a single net.

Read again what I wrote.  I am talking about REFLECTIONS, which is why you 
match them.
The tolerance from the T to the destination is critical because of this.  This 
is why you can 
have a global constraint (CPU to the memory) far more relaxed than the T to the 
memory.

View in courier:
                            B
                  ___________  MEM1
                 |
      A          |
CPU--------------|T
                 |          C
                 |___________  MEM2


So,  A-B == A-C  . This is usually a loose tolerance for an address bus.  You 
can use GLOBAL constraints for this in a relative propagation delay, all 
combined into the same matched group.

And,  B-T == T-C . This is usually a lot tighter, for reasons given. This can 
be a LOCAL constraint and it does not reference any other address line.



> If the tolerances are not matched because they seen ridiculous,
> and the board doesn't work - guess what the chip manufacturer is
> going to point at?  That's right - the poor design that didn't
> follow their specs.

My point is, where do these length match numbers come from?  

The come from the people who design the silicon.  They are not just random 
numbers.

These things
aren't spec'd in the datasheets, directly, typically...though some do.  If
the datasheet says length match to 100 mils, then of course, do it (even
though some datasheets are simply silly in their length match requirements,
but I agree...you do what the manufacturer specs).  But if no, you need a
way to understand first if you need to length match, and second how to
calculate what to length match to.  As opposed to just guessing that 50 mils
seems like it's good enough.  Overspecing something like this can make the
PCB layout job an order of magnitude harder, and can even cause problems
elsewhere, like having excess trace that can lead to yet another set of
problems.  What you have to do is keep the eye open sufficiently to meet the
specified setup and hold over the operating range of the parts.  And allow
some room.

Yes, it does make our job harder.  

> My point is that sometimes the maths for loose tolerances may
> make sense but there are other factors that go beyond the basics.

Well, %2 of frequency isn't really a loose tolerance!  I chose %2 to show
what frequency a 50 mil tolerance would could be used for.  It's a ballpark.
If the signaling that was being length matched were, for example, 200MHz,
then there is reason to question the 50 mils.

> As an absolute coincidence, my colleague just informed me that
> the new datasheet for our QDR ram has halved the tolerance for
> the address to +/- 250 mils (internal layers).  I would tend to
> trust them; obviously they know something we don't.  (Yes, I know
> that address lines generally have a looser tolerance than data
> and clocks.)

+/- 250 mils is 500 mils...lots of room, and sounds about right.  Far better
than trying to length match to 50 mils!


Read what I wrote about t-based topologies, and exactly where you need tight 
tolerances in certain areas.


> Speaking of clocks, they should almost always be
> the target unless otherwise specified.

IF there is a clock.  Not all "busses" have clocks.

For goodness sake, don't be so pedantic.

> I'm sure Soledad appreciates your comments, but this wasn't what
> he was asking.

I know that wasn't what he was asking, but he did say he was given a length
match of 50 mils, and I wanted to understand why.  For the reasons I've
stated, that most people don't know what it is they are specifying,
especially when I see a spec like this.  I also asked specifically for more
information on what he was doing...so I could make a more informed reply to
his situation.

Previous comment struck by RM out due to misreading:
"No he didn't.  He wanted to know HOW to do it, and gave the figures."
My apologies for this bit.
 

Regards,

Austin

-----------------------------------------------------------
To subscribe/unsubscribe: 
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx 
with a subject of subscribe or unsubscribe

To view the archives of this list go to 
http://www.freelists.org/archives/icu-pcb-forum/ 

Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx 
-----------------------------------------------------------
NOTICE: This message contains privileged and confidential
information intended only for the use of the addressee
named above. If you are not the intended recipient of
this message you are hereby notified that you must not
disseminate, copy or take any action in reliance on it.
If you have received this message in error please
notify Allied Telesis Labs Ltd immediately.
Any views expressed in this message are those of the
individual sender, except where the sender has the
authority to issue and specifically states them to
be the views of Allied Telesis Labs.
-----------------------------------------------------------
To subscribe/unsubscribe: 
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx 
with a subject of subscribe or unsubscribe

To view the archives of this list go to 
http://www.freelists.org/archives/icu-pcb-forum/ 

Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx 
-----------------------------------------------------------


NOTICE: This message contains privileged and 
confidential
information intended only for the use of the addressee
named 
above. If you are not the intended recipient of
this message you are hereby 
notified that you must not
disseminate, copy or take any action in reliance 
on it.
If you have received this message in error please
notify Allied 
Telesis Labs Ltd immediately.
Any views expressed in this message are 
those of the
individual sender, except where the sender has the
authority 
to issue and specifically states them to
be the views of Allied Telesis 
Labs.


_________________________________________________________________
Climb to the top of the charts! Play the word scramble challenge with star 
power.
http://club.live.com/star_shuffle.aspx?icid=starshuffle_wlmailtextlink_jan

Other related posts: