[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

Soledad,

I am assuming this will go to specctra, the constraint manager from what I know 
is just a GUI front end for a .do file generator.

This is an Xnet (extended net) where there is a virtual pin at the t branch 
point.  You are going to match the trunk of the t + branch1 = length of data to 
device 1, t+branch2 = length device2

Is this DDR?  dont forget clock and strobe...

Randy

> Subject: [PCB_FORUM] Re: Allegro V6.01 Constraint  Manager
> Date: Wed, 27 Feb 2008 14:35:58 -0800
> From: SAttia@xxxxxxxxxxxxxx
> To: icu-pcb-forum@xxxxxxxxxxxxx
> 
> Hi Austin,
> 
> 
> 
> To give you more information; we have a CPU feeding 14 address lines to
> two memory devices (upper memory device & lower memory device).  Our
> data bus is 32 bits wide.  16-bits of the data go to the upper memory
> devices and the other 16-bits go to the lower memory device.  Now, your
> explanation below make good sense for the data lines (thank for the
> info), what about the address lines?  The address lines must be the same
> length from CPU to the "T" point.  The "T" point to each of the memory
> devices also must match.  How would you do that?
> 
> Thanks again for your time and effort, 
> Soledad
> 
> 
> 
> 
> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
> Sent: Wednesday, February 27, 2008 1:54 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Allegro V6.01 Constraint Manager
> 
> Hi Soledad,
> 
> >   Logic
> >     -net schedule RMB insert T (this should be the midpoint of route
> >  Setup Constraints
> >     Relative propagation delay
> >      Select net create pin pair
> >         Create match group
> 
> To add to this...
> 
> Without knowing more about your application, I don't know if you care
> about
> that there is length matching between the source and the "T", and I'll
> assume not.  Setup a pinpair from source to destination 1 and source to
> destination 2 for each net, and put them all in the same length match
> group.
> You shouldn't need any pinpairs containing the T.
> 
> As a note on length matching.  A 50 mil length match with a propagation
> of
> 166ps/inch would be a length match of about 8.3ps length match.  If you
> were
> length matching to %2 of the frequency (which is quite "tight"), that
> would
> be a frequency of 6GHz!
> 
> Why I question the 50 mil length match, is sometimes, engineers aren't
> really sure how to calculate length match tolerance, and they come up
> with
> these really unnecessary tolerances.  It isn't really that hard to
> calculate.  You just have to know the frequency, and to what percent you
> need, or know what the amount of time is the design can tolerate.  What
> the
> design can tolerate is derivable from the spec sheets of what is being
> interfacing to...but %2 of the frequency is a pretty good (and tight)
> rule
> of thumb IMO.  Calculate the length delay using 166ps/inch (typical for
> FR-4) or what ever the proper prop. delay for your material is.
> 
> For example, if you are interfacing to 333MHz DDR, it's actually a rate
> of
> 666MHz (double data rate...as each edge is used), and say you want to
> use a
> %2 tolerance.  %2 of 666MHz is 1/(.02 * 666MHz) = 75ps, and 75ps /
> 166ps/inch = .45 inches.  If you use a target (a clock) you can
> typically
> use +/- 450 mils, making length matching and routing MUCH easier.
> 
> Regards,
> 
> Austin
> 
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