[PCB_FORUM] Re: Allegro V6.01 Constraint Manager

Austin

I think you have to be careful giving advice on tolerances.  They are most 
definitely this tight in many circumstances.  

An example of this is the crossover period for differential '+' and '-' pairs.  
A mismatch here will cause an imbalance in the ground return causing both SI 
(crosstalk in this case) and possibly EMC problems, not to mention problems at 
the receiver.  We typically match to less than +/- 10% of the rise time, 
although we look at each case independently.

In this case, the 'T' based memory topologies are very particular in matching 
from the t-point to each memory device.  It's not so much the timing you'll 
worry about - it's the reflections that don't cancel each other out.  (Again, 
SI and/or EMC.)

If the tolerances are not matched because they seen ridiculous, and the board 
doesn't work - guess what the chip manufacturer is going to point at?  That's 
right - the poor design that didn't follow their specs.  The worst thing that 
then happens is the software on the processor can't be tuned enough to 
compensate (tuning depending on the type of memory used.)

My point is that sometimes the maths for loose tolerances may make sense but 
there are other factors that go beyond the basics.

As an absolute coincidence, my colleague just informed me that the new 
datasheet for our QDR ram has halved the tolerance for the address to +/- 250 
mils (internal layers).  I would tend to trust them; obviously they know 
something we don't.  (Yes, I know that address lines generally have a looser 
tolerance than data and clocks.)  Speaking of clocks, they should almost always 
be the target unless otherwise specified.

One final note on memory devices.  They usually go though die shrinks more than 
any other type of silicon, usually with little or no notice to the user.  I've 
seen this kill older designs because the tolerance was too relaxed in the 
initial design of the board.

I'm sure Soledad appreciates your comments, but this wasn't what he was asking. 
 

Regards,
Richard

  
__________________________
Richard Moffat
PCB CAD Team Leader
Allied Telesis Labs
ph. +64 (3) 3393000
richard.moffat@xxxxxxxxxxxxxxxxxxx

>>> "Austin Franklin" <allegrolist@xxxxxxxxxxxx> 28/02/2008 10:53 a.m. >>>
Hi Soledad,

>   Logic
>     -net schedule RMB insert T (this should be the midpoint of route
>  Setup Constraints
>     Relative propagation delay
>      Select net create pin pair
>         Create match group

To add to this...

Without knowing more about your application, I don't know if you care about
that there is length matching between the source and the "T", and I'll
assume not.  Setup a pinpair from source to destination 1 and source to
destination 2 for each net, and put them all in the same length match group.
You shouldn't need any pinpairs containing the T.

As a note on length matching.  A 50 mil length match with a propagation of
166ps/inch would be a length match of about 8.3ps length match.  If you were
length matching to %2 of the frequency (which is quite "tight"), that would
be a frequency of 6GHz!

Why I question the 50 mil length match, is sometimes, engineers aren't
really sure how to calculate length match tolerance, and they come up with
these really unnecessary tolerances.  It isn't really that hard to
calculate.  You just have to know the frequency, and to what percent you
need, or know what the amount of time is the design can tolerate.  What the
design can tolerate is derivable from the spec sheets of what is being
interfacing to...but %2 of the frequency is a pretty good (and tight) rule
of thumb IMO.  Calculate the length delay using 166ps/inch (typical for
FR-4) or what ever the proper prop. delay for your material is.

For example, if you are interfacing to 333MHz DDR, it's actually a rate of
666MHz (double data rate...as each edge is used), and say you want to use a
%2 tolerance.  %2 of 666MHz is 1/(.02 * 666MHz) = 75ps, and 75ps /
166ps/inch = .45 inches.  If you use a target (a clock) you can typically
use +/- 450 mils, making length matching and routing MUCH easier.

Regards,

Austin

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