[PCB_FORUM] Re: Allegro 15.1: Shorting nets

Also note in version 15.1 The net_short property is added as a comment to
the IPC-356 netlist.
Another compelling reason  to use this method when it applies.

Gerry

-----Original Message-----
From: anthony.cosentino@xxxxxxxxxxx
[mailto:anthony.cosentino@xxxxxxxxxxx]
Sent: Thursday, August 26, 2004 3:20 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Allegro 15.1: Shorting nets



Jim,
Here is the explanation from the help menu on the use of NET_SHORT:
The NET_SHORT property, attached to a pin or via, lets you connect two
nets, such as GND and AGND, to a common pin or vias without a DRC error.
This property allows contact between two planes that have different net
names and prevents a flagged or reported DRC error.
A DRC is reported if any connect lines other than the net of the actual
pin, touch the origin point of the actual pin. The actual pin (or via) does
not report a DRC for any logic objects that touch it.

The syntax of the NET_SHORT property is:
<net 1>:<net 2>:....
For example:
NET_SHORT = GND1 : GND2 : GND3

Thanks
Tony Cosentino
Tekelec - PCB Design Engineer
5200 Paramount Parkway
Morrisville, NC 27560
919-460-3656 Work
919-414-2083 Cell
anthony.cosentino@xxxxxxxxxxx
www.tekelec.com




                      "J Wages"
                      Sent by:                 To:
<icu-pcb-forum@xxxxxxxxxxxxx>
                                               cc:
                                               Subject: [PCB_FORUM] Allegro
15.1: Shorting nets
                      08/26/2004 03:24
                      PM
                      Please respond
                      to icu-pcb-forum






Hey folks. Hopefully a simple question. Does Allegro 15.1 now have the
ability to short two nets together without creating a DRC error? I want
to short a digital ground plane with another isolated plane, but they
both have separate net names. I know I can do it by adding a feature
that will short the nets together using a non-etch layer during artwork
extraction, but that will cause an error at the fab end. Isn't there a
property I can add to a shape or via or pin?
Thanx in advance

Jim S. Wages / SR. PCB Layout Designer:
(919) 484-2963

-----Original Message-----
From: Schwartz, Jerome [mailto:jschwa01@xxxxxxxxxx]
Sent: Thursday, August 26, 2004 10:37 AM
To: 'icu-pcb-forum@xxxxxxxxxxxxx'
Subject: [PCB_FORUM] Re: strange characters in gerbers

Jan,

I tried: http://www.freedict.com/onldict/lat.html
Hillbilly does not translate.

 Regards,
      Jerry Schwartz, CID+
      IPC Certified Designer
     "May The Schwartz Be With You."

Designer 3
Harris Corporation GCSD              Voice (321)-727-5474
P.O. Box 37, MS 1/9843               Fax   (321)-727-6007
Melbourne, FL 32902-0037             Pager (321)-690-9797
mailto:Jerome.Schwartz@xxxxxxxxxx
http://www.harris.com




-----Original Message-----
From: Noble, Jan [mailto:jan.noble@xxxxxxxxx]
Sent: Thursday, August 26, 2004 11:26 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: strange characters in gerbers


Sam,
Your English is fine.  Welcome to the group.  HillBilly is my second
language.
:-))) Does anyone have a Latin translation for HillBilly?

Jan Noble
Intel Corporation
DuPont Board Development
253-371-6197

Cum catapultae proscriptae erunt tum soli proscripti catapultas habebunt

-----Original Message-----
From: sjcharles@xxxxxxx [mailto:sjcharles@xxxxxxx]
Sent: Thursday, August 26, 2004 8:22 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] strange characters in gerbers

Group,

I'm using the 15.2 cadence, and I'm generating gerbers. I'm seeing extra
characters in gerbers, but are not visible when I dislay the fab
drawing. I've
enable all layers and don't see these characters. Any ideas?

Please excuse my unsophisticated english.
Sam

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