[ibis-macro] Re: What I think BIRD145 is try to accomplish is ...
- From: Feras Al-Hawari <feras@xxxxxxxxxxx>
- To: "wkatz@xxxxxxxxxx" <wkatz@xxxxxxxxxx>, IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
- Date: Wed, 15 Feb 2012 01:28:19 -0800
Hello Walter,
The main goal of BIRD 145 is to directly cascade and call an IBIS I/O model
(standard VI/VT based model or an [External Model]) with an [External Circuit]
that could be a represenation of ODT, RDL, or package. Based on that, for
example, the [External Circuit] could reference an IBIS/ISS subckt that
contains your suggested ladder RC circuit.
So BIRD 145 would allow you to directly connect your ladder RC circuit
(encapsulated inside the [External Circuit]) to its corresponding buffer model
using the new [Model Call] subparameter. To accomplish the previous goal based
on the current IBIS spec you need to: 1) encapsulate the b-element inside a
subckt, 2) reference that b-element subckt from an [External Circuit], 3)
connect [External Circuit] that references the I/O model to the [External
Circuit] that references the ladder RC circuit. It is obvious that these steps
are cumbersome especially when the developer could just directly call the
desired IBIS I/O model without the need to develop a SPICE-like wrapper as well
as an [External Circuit] section.
Based on the above, the goal of BIRD 145 is different from your proposal below.
Thanks,
Feras
________________________________
From: Walter Katz [wkatz@xxxxxxxxxx]
Sent: Tuesday, February 14, 2012 6:24 PM
To: IBIS-ATM; Feras Al-Hawari
Subject: What I think BIRD145 is try to accomplish is ...
Feras,
I think the idea behind BIRD145 is similar to what Michael Mirmak proposed
several years ago, and what Randy Wolf discussed at the DesignCon IBIS Summit.
Both Randy and Michael wanted the ability to add a ladder RC circuit at the
output pad of the buffer. This is a real requirement that SiSoft has
implemented using an IBIS keyword Final_Stage, FinalStageDiff:
Final_Stage <typ|min|max> <ISS file name> <ISS subckt name>
and
Final_Stage_Diff <typ|min|max> <ISS file name> <ISS subckt name>
These are either a 2 port subckt (Final_Stage) or a 4 port subckt
(Final_Stage_Diff), that is inserted between the pad(s) of the B element and
the pad end(s) of the package).
Would this satisfy your IC Vendor modeling requirements? What other ports would
need to be included in this subckt?
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
Phone 303.449-2308
Mobile 720.333-1107
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