[ibis-macro] Outline of proposed [Diff Pin Model] [Diff Model] Bird
- From: "Walter Katz" <wkatz@xxxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Mon, 26 Nov 2007 10:50:53 -0500
All,
The following is a review of the structure that I would expand into a full
BIRD. This only supports the existing Tx and Rx differential IBIS
parameters.
I change the example to be more generic, and use an I/O instead of an Input.
I also removed [Model Selector], although it still can apply to both [Model]
and [Diff_model]
Example still has illegal [End ?] and indentation to make hierarchy clearer.
I would like to resolve some technical decisions (in red), and get agreement
on the proposed structure before formatting this into a BIRD. All of the
other new items such as derating, tVAC, LTI models, redefinition of
Tdiffslew rules, min/max common mode voltage rules, and eye template would
be in a separate BIRD.
Walter
Existing implementation
-----------------------
[Component] MEM
[Manufacturer] SiSoft
[Pin] signal_name model_name R_pin L_pin C_pin
E8 DQS+ DQS 41.35m 1.55nH 0.13pF
F8 DQS- DQS 42.93m 1.55nH 0.12pF
[End Pin]
|
[Diff_pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
E8 F8 .250V 0ns -50ps 50ps
[End Diff_pin]
|
[End Component]
|
[Model] DQS
Model_type I/O
? normal single pin IBIS stuff
[Receiver Thresholds]
Vcross_low = 0.675V
Vcross_high = 1.125V
Vdiff_ac = 500mV
Vdiff_dc = 250mV
Tdiffslew_ac = 5.000ns
[End Receiver Thresholds]
? normal single pin IBIS stuff
[End Model]
[End]
Proposed implementation
-----------------------
[Component] MEM
[Manufacturer] SiSoft
[Pin] signal_name model_name R_pin L_pin C_pin
E8 DQS+ DQS 41.35m 1.55nH 0.13pF
F8 DQS- DQS 42.93m 1.55nH 0.12pF
[End Pin]
|
[Diff_pin_model] inv_pin diff_model
E8 F8 DQS_DIFF
[End Diff_pin]
|
[End Component]
|
[Model] DQS
Model_type I/O
? normal single pin IBIS stuff (exclude differential [Receiver Thresholds]
stuff)
[End Model]
|
[Diff_model] DQS_DIFF
Model_type Pseudo_Differential_I/O
|
Single_ended_capable True
|
| Buffer model
|
| Model
Single_ended_model DQS
| or
Active_high_model DQS
Active_low_model DQS
| and? /or
[External Model]
?
[End External Model]
|
| Transmit active high/low skew
|
[Transmit Thresholds]
tdelay_typ = 0ns
tdelay_min = -50ps
tdelay_max = 50ps
| or
tdelay 0ns -50ps 50ps
[End Transmit Thresholds]
|
| Receiver analysis
|
[Algorithmic Model]
Executable Windows_VisualStudio_32 dqs.dll dqs.ami
[End Algorithmic Model]
|
[Receiver Thresholds]
Vcross_low = 0.675V | Minimum common mode voltage at differential signal
crossing 0V
Vcross_high = 1.125V | Maximum common mode voltage at differential signal
crossing 0V
Vdiff = 250mV
Vdiff_ac = 500mV
Vdiff_dc = 250mV
Tdiffslew_ac = 5.000ns
[End Receiver Thresholds]
|
|
[End Diff_model]
|
[End]
Precedence Rules:
[Diff_pin_model] takes precedence over [Diff_pin]
If [Diff_pin_model], differential parameters [Receiver Thresholds] in
[Model] are ignored
Active_high_model and Active_low_model take precedence over
Single_ended_model
Issues to resolve:
Format of tdelay
Allow both [External Model] and Single_ended_model (leave choice to EDA
tool)
Allow multiple [External Model] in a [Diff_model]
In one IBIS file there can be
multiple speed grades
multiple ODT
multiple analog models
IBIS
Verilog
VHDL
Spice
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