[ibis-macro] Re: New developments regarding PWL sources and B-element
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Fri, 9 Sep 2005 13:39:46 -0700
Mike,
Thanks for your comment. I think I should clarify something.
We will NOT be able to do it like HSPICE's B-element does it,
reference an IBIS file and the [Model] name inside it, and
then parse that to find the IV / Vt curve keywords and the
rest of the parameters. I just found out that Verilog-A(MS)
simply does not have the capability to read and parse files
like that. (This could all be done in VHDL-AMS, by the way).
Having said that, regardless of what I was saying in the previous
message, the Verilog-A(MS) IBIS_B building block would require
that the user extracts the IV and Vt tables from the IBIS file
into individual data files, which can be referenced by the
$table_model keyword, or array parameter passing syntax.
Now, the $table_model keyword has two formats, one that uses
a file name, and the other that uses arrays for its input.
If we use the file name, it must be hard coded, it cannot be
parameterized. This is why we were talking about the user
having to make multiple copies of the IBIS_B building block
for each instance of it.
However, I realized that if I used the array format for the
$table_model, I can pass the arrays as parameters into the
IBIS_B building block at the time of instantiating it. This
would eliminate the need for duplicating the IBIS_B building
block for each instance. The array sizes do not have to be
the same between each instance of the IBIS_B building block.
This is what I was writing about in my last message. To me
this seems to be much cleaner than the previous method.
The data files would be about the same for both methods, they
would have to be individual files for every single IV and Vt
table. The second method would require some additional syntax
to obey the array assignment rules, but these are mostly
punctuation characters, such as "{", "}" and commas. The
question is, whether the slight addition of such syntax in
the data files is a bigger deterrent then having to duplicate
the entire IBIS_B building block for each instance.
One thing that I forgot to mention in my last message is that
in addition to the data, the length of the data would also
need to be passed. Verilog-A(MS) doesn't have a keyword to
return the size of an array, it must be given. So every time
someone makes an IV or Vt table file, they will have to count
the number of elements (rows) and pass that number into the
IBIS_B building block also. Annoying, but manageable.
Thanks,
Arpad
===============================================================
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of Mike LaBonte (milabont)
Sent: Friday, September 09, 2005 1:10 PM
To: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Re: New developments regarding PWL sources and B-element
I don't get a good feeling about this. My sense is that users will want
to specify only the file name and model name, and will be put off if we
appear to be proposing something that is difficult to explain. My
opinion is that it's not worth the price if we add ugliness so that we
can retain the elegance of a single buffer definition. And how would
this translate to HSPICE, for example, if the buffer instantiation does
not have a file name and model name?
That said, I can't quite picture what it would look like. And please
correct me if I appear to be making false assumptions.
Mike
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