[ibis-macro] Minutes for the 30 may 2006 ibis-macro meeting

From: "Mike LaBonte \(milabont\)" <milabont@xxxxxxxxx>
To: <ibis-macro@xxxxxxxxxxxxx>
Date: Tue, 13 Jun 2006 10:35:26 -0400

Minutes for the 30 may 2006 ibis-macro meeting are attached.
 
Mike

Meeting date: 30 may 2006
Members (asterisk for those attending):
*Arpad Muranyi, Intel Corp.
*Bob Ross, Teraspeed Consulting Group
*Todd Westerhoff, Cisco Systems
*Mike LaBonte, Cisco Systems
Paul Fernando, NCSU
Barry Katz, SiSoft
Walter Katz, SiSoft
Ken Willis, Cadence Design Systems
*Ian Dodd, Mentor Graphics
*Lance Wang, Cadence Design Systems
Richard Ward, Texas Instruments
Doug White, Cisco Systems
Sanjeev Gupta, Agilent
*Joe Abler, IBM
John Shields, Mentor Graphics

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Review of ARs:

- no ARs

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Discussion of Mike's encryption key chain diagram

- Who delivers the keys?
  - Model vendor

- Is this for VHDL or Verilog or both?
  - actual language keywords might be different

- Is Envelope key vendor-specific or product-specific
  - probably product

AR: Mike forward diagram to John Shields for comments

Cisco working on a coordinated approach to serial link design
- Started with EDA tool requirements.
- Moved onto model vendor requirements.
  - Need to have non-proprietary models that are interoperable.
- May be difficult to share internal documents.

Back to where we got stuck; trying to obtain advanced models
to see what is needed to make it non-proprietary.

AR: Ian ask Gary Pratt about progress getting models

People have differing opinions about whether AMS can model receivers
with DFE control algorithms.
- Performance good enough to simulate long patterns may be a problem.
- There will be a big transition from SPICE. It better have a big enough
  jump in performance to be worthwhile.

Down the road: crosstalk cancellation. Probably need to get beyond
circuit models.

What is the barrier?
- language?
- modeling style?
- tools?

People gravitatiing toward Verilog AMS approach because of the notion
that serdes design is "out there".

Higher level of abstraction would make development easier.
- People using Matlab today.

Fast convolution algorithms assume linearity.
- But systems really are pretty linear
- Maybe not for buffers.

Channel analysis approach:
- Get pulse response with time domain simulation.
- Driver characteristics must not change:
  - Could have a selection of characterizations available.
  - Systems becoming multiple-state linear.
  - Gate feedback makes them non-linear.
  - Mentor tool checks linearity.

What we care about is system design:
- Error rate:
  - Modeled with system tools today.
  - IBM writing models in C.
  - Intel using Matlab.
- Standards compliance:
  - At 3GHz meeting eye mask limits will do it.

VHDL can simulate 100-150 cycles, but not 1 billion cycles

IBM: need to simulate 10 million bits for crosstalk
- Simulation model assumes linearity, but allows end-to-end analysis.

Does it have to be written in C or Matlab?
- SPICE has 1-to-1 mapping, design process is not upset.
- If other formats have to be created, people will not want to keep
  them in sync.
- Matlab has pretty good ready-made functions.

Todd's two questions:
- Do the AMS languages have the constructs we need?
  - Richard says yes.
  - Joe is worried about performance.
- Will people do it?

Can IBIS deliver buffer characterizations for input to tools like Matlab?
- Buffer has to be characterized with exact interconnect.
- This doesn't work if the buffer changes when reflection hits it.

Next week discuss inputs to Matlab model

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Next meeting: Tuesday 06 Jun 2006 12:00pm PT

[ibis-macro] Minutes for the 30 may 2006 ibis-macro meeting

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