[ibis-macro] Re: A_to_D and D_to_A

Arpad,

Thank you very much.

James


-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] 
On Behalf Of Muranyi, Arpad
Sent: Thursday, April 12, 2012 2:53 PM
To: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Re: A_to_D and D_to_A

James,

No, there is no restriction in IBIS like that.  The output of
the model in [External Model] or [External Circuit] can do
anything the model maker wants.  In fact, even regular [Model]s
can go the opposite way too, if they include the “Polarity”
subparameter with the “Inverting” argument.

| The Polarity subparameter can be defined as either
| Non-Inverting or Inverting, and the Enable subparameter can be
| defined as either Active-High or Active-Low.

(pg. 35)

Arpad
==================================================================

From: James Zhou [mailto:james.zhou@xxxxxxxxxx]
Sent: Thursday, April 12, 2012 4:00 PM
To: gedlund@xxxxxxxxxx; Muranyi, Arpad
Cc: ibis-macro@xxxxxxxxxxxxx; ibis-macro-bounce@xxxxxxxxxxxxx
Subject: RE: [ibis-macro] Re: A_to_D and D_to_A

Hi Arpad ,

Considering the native IBIS model using [Ramp] and [Rising/Falling Waveform] 
keywords, for a logic 0 to 1 transition at input of D_to_A, must the output 
ramp always be low to high? Similarly, for a logic 1 to 0 transition at input 
of D_to_A, must the output ramp always be high to low? I could not find any 
description in the Specification addressing this.

Thanks,
James Zhou


From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] 
On Behalf Of Gregory R Edlund
Sent: Thursday, April 12, 2012 1:50 PM
To: Arpad_Muranyi@xxxxxxxxxx
Cc: ibis-macro@xxxxxxxxxxxxx; ibis-macro-bounce@xxxxxxxxxxxxx
Subject: [ibis-macro] Re: A_to_D and D_to_A

Got it now.  Thanks!

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901



"Muranyi, Arpad" ---04/12/2012 03:35:32 PM---Greg, Your last sentence it the 
answer.

From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
Date: 04/12/2012 03:35 PM
Subject: [ibis-macro] Re: A_to_D and D_to_A
Sent by: ibis-macro-bounce@xxxxxxxxxxxxx
________________________________________



Greg,

Your last sentence it the answer.

The [Ramp] or V-t curve in the IBIS [Model] is not a stimulus
to the model.  The beginning of the [Ramp] or the t=0 for the
V-t curve is an “event” generated by the EDA tool to get the
transition in the model going.  These events are the stimulus
to the model.  These events are not voltage waveforms, these
are events which tell the model:

“start your low to high transition (or high to low) transition”.

This is why we think of them as a “digital” stimulus.  Even if
you think of the B-element of the famous SPICE tool of all times,
which uses a voltage waveform for its input, that input has a
threshold associated with the internal logic.  When the input
waveform crosses that threshold, the internal algorithm creates
an event to mark the t=0 for the IBIS [Ramp] or V-t tables which
are provided with the .ibs file.

I hope this clarifies things for you.

Thanks,

Arpad
===================================================================

From: Gregory R Edlund [mailto:gedlund@xxxxxxxxxx]
Sent: Thursday, April 12, 2012 3:12 PM
To: Muranyi, Arpad
Cc: ibis-macro@xxxxxxxxxxxxx; ibis-macro-bounce@xxxxxxxxxxxxx
Subject: Re: [ibis-macro] Re: A_to_D and D_to_A

Arpad,

Thanks for the explanation.  I'm still confused, though.  I always thought that 
simulators used an analog stimulus function for IBIS models, either in the form 
of a ramp or VT curve.  (Let's forget about external models for the time 
being.)  Is there something else going on behind the scenes that I'm not aware 
of?  Maybe a digital stimulus "kicks off" the ramp or VT curve?

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901



"Muranyi, Arpad" ---04/12/2012 12:07:25 PM---Greg, [External Model] or 
[External Circuit] basically instantiates

From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
Date: 04/12/2012 12:07 PM
Subject: [ibis-macro] Re: A_to_D and D_to_A
Sent by: ibis-macro-bounce@xxxxxxxxxxxxx
________________________________________




Greg,

[External Model] or [External Circuit] basically instantiates
a VHDL-AMS, Verilog-AMS, Verilog-A, or SPICE model.  The last
two can only have analog terminals (ports) on their interface.
The first tow may have analog or digital terminals (ports),
and it is up to the model maker to decide who they connect
their model to the outside world.

In IBIS, we assume that the EDA tool’s stimulus is purely
digital (whether this is true in reality or not).  So the
stimulus for a driver, D_drive and the enable signal, D_enable
are considered a logic ‘1’ or ‘0’, not a voltage.

In order to drive the terminals of a purely analog model, you
need to have a D_to_A converter.  The drawing you are asking
about tries to illustrate how these converters are inserted
(automatically) by the EDA tool between its stimulus and the
analog terminals of the model.

Does this answer your question?

Thanks,

Arpad
================================================================
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] 
On Behalf Of Gregory R Edlund
Sent: Thursday, April 12, 2012 11:49 AM
To: ibis-macro-bounce@xxxxxxxxxxxxx; ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] A_to_D and D_to_A

In reading through the BIRDs that have been tabled, I found myself going back 
to the original [External_Model] syntax from IBIS 4.2.  I'm having a hard time 
wrapping my head around the whole "analog-to-digital" thing.  Can anybody give 
me a simple example of when you might need a model like the one described in 
the 4.2?

|             +==================================================+
|             |                    "Model Unit"        +--------+|
|             |  +--------+                            |        ||
| D_receive --|-<| A_to_D |--<(analog receive ports)--<|        ||-- A_puref
|             |  +--------+                            | A pure ||
|             |                                        | analog ||-- A_pdref
|             |  +--------+                            |  I/O   ||
|   D_drive --|->| D_to_A |-->(analog drive ports)  -->| buffer ||-- A_signal
|             |  +--------+                            | model  ||
|             |                                        |        ||-- A_pcref
|             |  +--------+                            |        ||
|  D_enable --|->| D_to_A |-->(analog enable ports) -->|        ||-- A_gcref
|             |  +--------+                            |        ||
|             |                                        +--------+|
|             +==================================================+
|      Model Unit consists of SPICE, VHDL-A(MS), Verilog-A(MS) code plus
|                        A_to_D and D_TO_A converters
|            (references for D_to_A and A_to_D converters not shown)
|
| Figure 6: An analog-only Model Unit, using an I/O buffer as an example

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901

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