[hashcash] Re: stamp speeds on new hardware

That is one core on the athlon64 so a single athlon64 x2 with both
cores slightly outperforms the 2Ghz G5.

Remind me to re-run this on my G5 using a version compiled with GCC4, if possible. I've found with other programs that GCC4 makes a huge difference to the G5, though much less on G3/G4. My G5 (thanks IBM) has two 2.3GHz CPUs, so should easily beat the A64 again.

However, compiling hashcash Altivec cores with GCC is proving to be very troublesome, especially under Linux, because the preprocessor expands the source to an insanely complex degree, and the compiler then chokes on it. I may need to rearrange things significantly to get around this problem, but I lack the time at present.

But I would think assembler targetted at the 64 bit athlon + any 64
bit mmx / sse variant should get a boost on a 64bit vs 32bit athlon?

There are two cases where running in 64-bit mode on the A64 should get a benefit:

- For scalar cores, simply compiling for 64-bit mode will help, because extra registers are available. I'm not sure, however, whether this will beat the existing MMX mode.

- In SSE2, the 64-bit mode gets double the registers as well. SSE2 may itself be twice as fast as MMX, because the registers are twice as wide. But it should still be slightly slower per clock/core than the G5, because the latter has some extra useful instruction types. I don't have any SSE2 hardware to implement such a core on.

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from:     Jonathan "Chromatix" Morton
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website:  http://www.chromatix.uklinux.net/
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