Christian Packmann wrote:
I could need a few volunteers now to run the benchmark on various systems and post/mail the results.
~> runme_haiku Benchmark: Haiku app_server bilinear copy Compile date: Jun 14 2009 14:38:02 GCC version: 2.95.3-haiku-081024 CPU vendor ID: GenuineIntel CPU: Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz SIMD instructions: MMX SSE SSE-Integer SSE2 SSE3 SSSE3 Can't lock process to CPU on this platform. Estimated CPUID/RDTSC overhead: 252 clock cycles. 10 runs per benchmark. -- Results -- Minimum Average Maximum # 1: 358992 371104 469404 - 'C, original' # 2: 331956 332840 337968 - 'C, precise' # 3: 350292 350571 350892 - 'C, precise DIV' # 4: 189048 190225 194904 - 'MMX/SSE' # 5: 177720 178263 182520 - 'MMX/SSE optim-test' # 6: 249084 249242 249624 - 'SSE2' # 7: 230040 230172 230496 - 'SSSE3' ~> sysinfo Kernel name: kernel_x86 built on: Jun 14 2009 14:33:00 version 0x1 2 Intel Core 2, revision 06f6 running at 2000MHz (ID: 0x00000000 0x00000000) CPU #0: "Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz" Type 0, family 6, model 15, stepping 6, features 0xbfebfbff FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CFLUSH DS ACPI MMX FXSTR SSE SSE2 SS HTT TM PBE Extended Intel: 0x0000e3bd SSE3 MONITOR DS-CPL EST TM2 CMPXCHG16B Extended AMD: type 0, family 0, model 0, stepping 0, features 0x20100000 NX 64 Power Management Features: L2 Data cache fully associative, 1 lines/tag, 64 bytes/line L2 cache: 4096 KB, 16-way set associative, 0 lines/tag, 64 bytes/line Inst TLB: 2M-bytes pages, 4-way set associative, 8 entries OR 4M, 4-way, 4 entries Inst TLB: 4K-bytes pages, 4-way set associative, 128 entries Data TLB: 4M-byte pages, 4-way set associative, 32 entries 64-byte Prefetching L1 Data TLB: 4K-bytes pages, 4-way set associative, 16 entries L1 Data TLB: 4M-bytes pages, 4-way set associative, 16 entries Unknown cache descriptor 0x49 L1 inst cache: 32 KB, 8-way set associative, 64 bytes/line Data TLB: 4K-bytes pages, 4-way set associative, 256 entries L1 data cache: 32 KB, 8-way set associative, 64 bytes/line CPU #1: "Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz" Type 0, family 6, model 15, stepping 6, features 0xbfebfbff FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CFLUSH DS ACPI MMX FXSTR SSE SSE2 SS HTT TM PBE Extended Intel: 0x0000e3bd SSE3 MONITOR DS-CPL EST TM2 CMPXCHG16B Extended AMD: type 0, family 0, model 0, stepping 0, features 0x20100000 NX 64 Power Management Features: L2 Inst cache fully associative, 1 lines/tag, 64 bytes/line L2 cache: 4096 KB, 16-way set associative, 0 lines/tag, 64 bytes/line Inst TLB: 2M-bytes pages, 4-way set associative, 8 entries OR 4M, 4-way, 4 entries Inst TLB: 4K-bytes pages, 4-way set associative, 128 entries Data TLB: 4M-byte pages, 4-way set associative, 32 entries 64-byte Prefetching L1 Data TLB: 4K-bytes pages, 4-way set associative, 16 entries L1 Data TLB: 4M-bytes pages, 4-way set associative, 16 entries Unknown cache descriptor 0x49 L1 inst cache: 32 KB, 8-way set associative, 64 bytes/line Data TLB: 4K-bytes pages, 4-way set associative, 256 entries L1 data cache: 32 KB, 8-way set associative, 64 bytes/line 2028216320 bytes free (used/max 117694464 / 2145910784) (cached 72118272) 129508 semaphores free (used/max 1564 / 131072) 3937 ports free (used/max 159 / 4096) 3954 threads free (used/max 142 / 4096) 2029 teams free (used/max 19 / 2048) Regards, Humdinger -- --=-=--=-=--=-=--=-=--=-=--=-=--=-=--=-=--=-=--=- Deutsche Haiku News @ http://www.haiku-gazette.de