[haiku-development] On timeslices and cycles

I'm writing a larger-than-expected piece to publish on the blog
regarding my latest developments on the scheduler, and there's
something bugging me. I have my opinion on this regard, but I'd like
to gather more diverse points of view from the developers.

What do you think of using timeslices (or time-based quanta) to
represent the period in which a thread is allowed to run before being
preempted in an age of CPUs clocking at extremes such as circa 200MHz
on embedded processors and 3GHz on higher-end desktops? Should the
quantum be computed based on the clock, instead of fixed at every N
miliseconds? If so, should it change if clock throttling kicks in?

What happens when you have asymmetric multiprocessors, like for
example in an hypothetical motherboard that can support both an Atom
and a Core processor on separate sockets? This is an unlikely example,
but there already exists research on this regard for desktop products,
and there *are* such products for embedded markets. A more familiar
example is "advanced" clock throttling where each core can be
throttled independently, such as in AM2+ Phenoms. AFAICT those are not
user-controllable (independently, I mean), but I see no reason why
future products can't have this feature.


So... What are your opinion?



Thanks,
A.

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