#5383: MTRR regression: AGP transfer inconsistencies -----------------------+---------------------------------------------------- Reporter: rudolfc | Owner: nobody Type: bug | Status: new Priority: normal | Milestone: R1 Component: - General | Version: R1/Development Keywords: | Blockedby: 5353 Platform: All | Blocking: -----------------------+---------------------------------------------------- Changes (by bonefish): * version: R1/alpha1 => R1/Development Comment: The Architecture Compatibility chapter reveals that the PCD and PWT flags have been introduced in the 486. Regarding the how to get your driver's RAM buffer working correctly: If WT is not acceptable for that, then on pre-P6 processors (i.e. the Pentium) the kernel will have to fall back to UC. No way around that. For Pentium III and later PAT+PCD+PWT can be used in combination with a single WB MTR. That leaves Pentium II and Pentium Pro (and supposedly the competition's equivalents). Either those are sacrificed for sake of simplicity, also using a single WB MTR with PCD+PWT and therefore having to resort to UC when WC is requested (which would also hold for the frame buffer!), or they continue to use MTRRs as best as possible, thus needing to be special-cased. -- Ticket URL: <http://dev.haiku-os.org/ticket/5383#comment:5> Haiku <http://dev.haiku-os.org> Haiku - the operating system.