[haiku-bugs] Re: [Haiku] #5383: MTRR regression: AGP transfer inconsistencies
- From: "bonefish" <trac@xxxxxxxxxxxx>
- Date: Tue, 16 Feb 2010 21:24:04 -0000
#5383: MTRR regression: AGP transfer inconsistencies
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Reporter: rudolfc | Owner: nobody
Type: bug | Status: new
Priority: normal | Milestone: R1
Component: - General | Version: R1/alpha1
Keywords: | Blockedby: 5353
Platform: All | Blocking:
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Comment(by bonefish):
Replying to [comment:3 rudolfc]:
> Thanks for the info. I did a quick read on the PTE bits and #5353: so if
you go that way that would mean that MTRR-WC in system RAM would not be
possible anymore on Haiku since the PWT bit only gives the options write-
trough and write back? (not write-combining)
Oh my, you're right. I guess I misread the WT for WC. So the method would
really only work with PAT support (i.e. for Pentium III and later), which
allows to select any memory type. There go my hopes to get rid of the MTRR
pain for good... :-/
> Since I cannot flush the ram buffer (partly) in userspace(?) write-back
isn't useable so the writing to cache can only be disabled indeed then to
get it working at all?
>
> Do I miss something? Is the driver correctly setup for this 1Mb buffer?
Should I modify something here or is this a problem that will be solved
elsewhere (kernel)?
This is really just a kernel problem. The driver is set up correctly.
Well, that is I don't know how things would need to work on pre-P6
processors, i.e. those that don't have MTRRs. Obviously on those one
cannot set the memory type for a RAM range to WC, anyway. I haven't found
any info on when the PTE caching bits had been introduced.
--
Ticket URL: <http://dev.haiku-os.org/ticket/5383#comment:4>
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