[ee_shoppahs] AMD in FL

Passing it on...

-------- Original Message --------
Subject:        Senior ASIC Design Verification
Date:   Tue, 17 Aug 2010 14:32:33 -0700 (PDT)
From:   Kal Luben (Linkedin Requests) <requests-noreply@xxxxxxxxxxxx>
To:     Nick Collins <ncollins3@xxxxxxxxx>



 LinkedIn

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*From:* Kal Luben

*Date:* 8/17/2010

*Subject:* Senior ASIC Design Verification

Hi Nick,
This is Kal Luben, I am a recruiter at AMD. We are looking for a couple of senior ASIC design verification engineers to work on our next generation GPU's with our group in Orlando, FL. Please let me know if you or an engineer you know may care to explore the position below? 

Best regards,

Kal

Responsibilities:
• Verification Plan (creation and ownership for execution of plan) for state-of-the-art graphics core hardware block level implementation. • Understand functionalities of design in architecture and design specifications. • Test environment design including all or parts of: test bench, block level test api, scoreboarding, directed and constrained random test cases, BFM, monitors and automatic checkers. • Creation and execution of Functional Coverage test plan; review plan with implementation team. 
• Support testing for DFP and DFT
• Responsible for all levels of verification for a block including RTL and gate level views. 
Requirements:
1. Major in CS or EE and have Master degree or higher
2. Three years or beyond working experience on ASIC design verification
3. Must be proficient in C++, OVM, SystemVerilog, CRV Perl/CGI, C-Shell, Verilog/VHDL, make/gmake, HTML, TCL/TK, PHP and debugging in Linux and Windows platforms.Good knowledge of Software Engineering. 4. Good to have graphics pipeline experience (College course using OpenGL/OpenCL/DX may be sufficient). 
5. Must be skillful in shell/perl/tcl/Makefile programming in linux OS.
6. Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools 
7. Good English hearing, speaking, reading and writing capabilities.
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