FreeLists / si-list / [SI-LIST] Re: internal time step too small error in transient analysis

[<vuk_borich@xxxxxxxxxxx>]

Hi Boli,

Send me the project and I'll try to help you. ADS 2004A is 4 generations =
old now, and there have been many, many improvements in the meantime, =
including significant improvements to divider simulation both in =
harmonic balance and transient.

Regards,

Vuk Borich
Operating Manager, A/RF Simulation and Models
Agilent Technologies, EEsof Division
408 553 2605

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of boli sudha
Sent: Tuesday, December 18, 2007 10:57 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] internal time step too small error in transient =
analysis

hi all,
         iam doing a project on WLAN synthesizer.iam using ADS 2004A. i =
have
designed individual blocks of VCO,divider blocks. for divider iam using
master slave flipflops. so initially i need to reset them, for that i =
used a
reset signal. if i run this  divider block it is running individually in
transient analysis. but if i integrate this block with VCO's output it =
is
giving internal time step error.  so i changed every  thing like below =
which
i got when i search  in google. but error is coming again .

1. Increase rise-time and/or fall time of the pulse
2. Increase ITL4 between 25 and 500, (default is 10)
3. Change TRAP method to GEAR
4. Change MAXORD to 3, 4, 5, and 6
5. Change TRTOL to 25 (default is 7)
6. Change LVLTIM from 2 to 1
7. Increase TNUM
8. Change ITL4 to 100
9. Reset above, and set these
RELTOL =3D 0.01
ABSTOL =3D 1.0e-9
VNTOL =3D 1.0e-4
LVLTIM =3D 1
METHOD =3D GEAR
MAXORD =3D 2
TNUM =3D "pick big number"
ITL4 =3D 100

can anybody help me please.


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