FreeLists / si-list / [SI-LIST] Re: : IBIS Vs SPICE matching issue

["Mike LaBonte (milabont)" <milabont@xxxxxxxxx>]

Sudhanshu,

It is very common to see a time shift between SPICE and IBIS waveforms
for the same buffer. An IBIS model gives the output behavior of a
buffer, but not the details of the predriver and it's delays. When
comparing them it is handy to have a waveform viewer that can time shift
waveforms.

If there are slope problems I would suggest looking at how C_comp is
derived. Even when all other IBIS data are determined by simulation, it
appears that C_comp is sometimes guessed. C_comp can be determined
through an AC simulation, but not all SPICE-to-IBIS tools do this. For
example, NCSU s2ibis does not.

The details of how simulators use IBIS information is up to each
simulator. Therefore there is no single authoritative source on how IBIS
is simulated. However, an example can be seen in the Macromodel Element
Library (http://www.vhdl.org/pub/ibis/macromodel_wip/), which has
example IBIS buffers written in VHDL-AMS and Verilog-A. Of course this
is source code, not a white paper.

Mike

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sudhanshu SINGH
Sent: Monday, December 10, 2007 10:55 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] : IBIS Vs SPICE matching issue

Hello All,

I sometimes observed that IBIS Vs SPICE matching issue.
IBIS data was  extracted from SPICE netlist simulation and printed in
iBIS format properly.
Stil there is some mismatch in SPICE netlist output and IBIS output.
Mismatch may be in form constant delay or in form of slower/faster
response as the output fall or rise.

- What are the reason for this and how it can be corrected?

- Also is there any documentation which tells how exactly all IBIS
tables (e.g. VI, rise VT, fall VT tables) are used in extracting output
behaviour of a circuit?

- how much accuracy is needed for IBIS usage point of view.

Thanks in advance.

Regards,
Sudhanshu



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