Date Index for si-list, 12-2005

[si-list] || [12-2005 Date Index] [12-2005 Thread Index]

[SI-LIST] IBIS question - nrpatel
[SI-LIST] Re: IBIS question - Tom Dagostino
[SI-LIST] Re: DC resistance of the Power Supply on PCB - Andrew Ingraham
[SI-LIST] Re: NEXT and FEXT: Question on relative levels - Grasso, Charles
[SI-LIST] Re: NEXT and FEXT: Question on relative levels - Dr. Howard Johnson
[SI-LIST] Re: NEXT and FEXT: Question on relative levels - Grasso, Charles
[SI-LIST] Mobile DDR specifications. - Sanchayan Sinha
[SI-LIST] pcb board capacitors - david stern
[SI-LIST] Re: pcb board capacitors - Fred Townsend
[SI-LIST] Re: pcb board capacitors - Paul Levin
[SI-LIST] stack up design with a field solver - Eric Bogatin
[SI-LIST] validation help - Mark Burford
[SI-LIST] Re: pcb board capacitors - Ken Cantrell
[SI-LIST] Re: pcb board capacitors - Dagmara Avanindra
[SI-LIST] Re: pcb board capacitors - Lee Ritchey
[SI-LIST] CR-5000 Lightning - mamontem
[SI-LIST] Re: CR-5000 Lightning - Walter Huang
[SI-LIST] Re: pcb board capacitors - Benner, Stuart (AGTE)
[SI-LIST] Re: pcb board capacitors - steve weir
[SI-LIST] Re: pcb board capacitors - Lee Ritchey
[SI-LIST] Impedance control - rana sadaf
[SI-LIST] Trace bandwidth - poornima poornima
[SI-LIST] Gigabit traces on Backplane - jain.nitin
[SI-LIST] Re: Impedance control - steve weir
[SI-LIST] Re: Gigabit traces on Backplane - steve weir
[SI-LIST] MLF packages - Vivek Chandra
[SI-LIST] Re: MLF packages - Gary Schneider
[SI-LIST] Re: Impedance control - Rich
[SI-LIST] Re: Gigabit traces on Backplane - Lee Ritchey
[SI-LIST] Signal Integrity, Package design project in Santa Clara - Kevin Pierpoint
[SI-LIST] Back of the envelope termination resistor calculation - Alex Horvath
[SI-LIST] Re: Back of the envelope termination resistor calculation - Dan Bostan
[SI-LIST] Re: Back of the envelope termination resistor calculation - Alex Horvath
[SI-LIST] Re: Trace bandwidth - Dennis Han
[SI-LIST] Re: MLF packages - Chandrakanth
[SI-LIST] Re: Back of the envelope termination resistor calculation - Yuming Cheng
[SI-LIST] Question of taking measurement. Thanks. - Peng Ye
[SI-LIST] Re: Question of taking measurement. Thanks. - Bill Wurst
[SI-LIST] Re: MLF packages - Ray Anderson
[SI-LIST] Re: MLF packages - Chandrakanth
[SI-LIST] Via inside SMD discrete - Naren Thesia
[SI-LIST] New Member - Chandrakanth
[SI-LIST] Application of copper tape for experimental use - Doug Smith
[SI-LIST] Re: Via inside SMD discrete - kfrobinson
[SI-LIST] Re: Question of taking measurement. Thanks. - Ihsan Erdin
[SI-LIST] Re: MLF packages - Andrew Ingraham
[SI-LIST] Re: Question of taking measurement. Thanks. - Andrew Ingraham
[SI-LIST] Re: Question of taking measurement. Thanks. - Tom Dagostino
[SI-LIST] High Aspect Ratio Problem in HFSS 9.0 - kundanchand chand
[SI-LIST] Re: Via inside SMD discrete - Symon
[SI-LIST] Re: Via inside SMD discrete - Symon
[SI-LIST] Use of Yahoo and other non-specific email accounts - Dr. Edward P. Sayre
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - dj rj
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Peterson, James F (FL51)
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Richard P EVANS
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Todd Westerhoff (twesterh)
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Rich
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Khan, Mohammad I
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Chris Cheng
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - art_porter
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Ravinder . Ajmani
[SI-LIST] Use of Yahoo and other non-specific email accounts - peter moldauer
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Allen Nejah
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Scott McMorrow
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - dj rj
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Todd Westerhoff (twesterh)
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Dagmara Avanindra
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Oscar Lang
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Chris Cheng
[SI-LIST] Microstrip/Stripline - Babid A
[SI-LIST] Re: Microstrip/Stripline - Tom Dagostino
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Tom Dagostino
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Sheena Mira-ato
[SI-LIST] Hi - jbtera77
[SI-LIST] USB waveform - Pradeep RSA
[SI-LIST] Re: USB waveform - Vijay S CHACHRA
[SI-LIST] Re: Microstrip/Stripline - Hassan O. Ali
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Hassan O. Ali
[SI-LIST] Re: Microstrip/Stripline - jain.nitin
[SI-LIST] Logic Analyzer headers XAUI & PCI-E - raja
[SI-LIST] Firewire 1394 eye mask - Ed Sayre III
[SI-LIST] Re: Hi - Lee Ritchey
[SI-LIST] Re: Firewire 1394 eye mask - Ray Anderson
[SI-LIST] Re: Microstrip/Stripline - Lee Ritchey
[SI-LIST] Re: Microstrip/Stripline - Lee Ritchey
[SI-LIST] Re: Logic Analyzer headers XAUI & PCI-E - Paul Taddonio
[SI-LIST] Re: Microstrip/Stripline - Loyer, Jeff
[SI-LIST] Re: Microstrip/Stripline - Chauhan, Prakash
[SI-LIST] Re: Microstrip/Stripline - jose_moreira
[SI-LIST] Reminder: IEEE EMCS Santa Clara Valley Chapter meeting, 12-13-05 - Ahmad Fallah
[SI-LIST] 4-port node numbering - Ray Anderson
[SI-LIST] Re: 4-port node numbering - Grossman, Brett
[SI-LIST] Re: 4-port node numbering - Clewell, Craig
[SI-LIST] Re: 4-port node numbering - Dunbar, Tony
[SI-LIST] Re: 4-port node numbering - Loyer, Jeff
[SI-LIST] Re: 4-port node numbering - Ray Anderson
[SI-LIST] effects of propagation time with respect to rise time - john matt
[SI-LIST] Re: 4-port node numbering - Aubrey_Sparkman
[SI-LIST] Re: Hi - ravindra varma
[SI-LIST] Re: effects of propagation time with respect to rise time - Lynne D. Green
[SI-LIST] Re: Use of Yahoo and other non-specific email accounts - Thomas McGonigle
[SI-LIST] Q on V_fixture in IBIS model. - Grasso, Charles
[SI-LIST] Re: Q on V_fixture in IBIS model. - Muranyi, Arpad
[SI-LIST] Re: 4-port node numbering - Bill Beale
[SI-LIST] Re: effects of propagation time with respect to rise time - Alex Horvath
[SI-LIST] development of test method standards to characterize probes - Nick Paulter
[SI-LIST] Re: 4-port node numbering - Grossman, Brett
[SI-LIST] Timing analysis - m har
[SI-LIST] Re: Q on V_fixture in IBIS model. - Andrew Ingraham
[SI-LIST] I/O Buffer in HSpice - nrpatel
[SI-LIST] Re: Timing analysis - Ihsan Erdin
[SI-LIST] PC debug port pinout? - Dr. Edward P. Sayre
[SI-LIST] Re: PC debug port pinout? - Ray Anderson
[SI-LIST] Re: PC debug port pinout? - Brian Schieck
[SI-LIST] Re: PC debug port pinout? - Dimiter Popoff
[SI-LIST] Impedance matching - Babid A
[SI-LIST] Impedance matching - Babid A
[SI-LIST] Re: Impedance matching - Andrew Ingraham
[SI-LIST] Re: Impedance matching - Suo, Ying (Ying)
[SI-LIST] GerbTool ACR question - Jim Antonellis
[SI-LIST] Re: DC resistance of the Power Supply on PCB - dgun
[SI-LIST] R: I/O Buffer in HSpice - Guasti Giovanni
[SI-LIST] Question about Echo cancellation testing - Jean_Pierre . Bouthemy
[SI-LIST] Re: Question about Echo cancellation testing - Christopher R. Johnson
[SI-LIST] Pin Type Scope ground - Alex Horvath
[SI-LIST] Re: Pin Type Scope ground - Lee Ritchey
[SI-LIST] Re: Pin Type Scope ground - Alex Horvath
[SI-LIST] Re: Pin Type Scope ground - Alex Horvath
[SI-LIST] Re: Timing analysis - Edi Fraiman
[SI-LIST] Microstrip/Stripline - Eric Bogatin
[SI-LIST] Re: Microstrip/Stripline - Ken Willis
[SI-LIST] Re: Microstrip/Stripline - Mike Heimlich
[SI-LIST] Adding a capacitance between 2 transmission lines - Matthias Bergmann
[SI-LIST] Antwort: Re: Adding a capacitance between 2 transmission lines - Matthias Bergmann
[SI-LIST] Antwort: Re: Adding a capacitance between 2 transmission lines - Matthias Bergmann
[SI-LIST] Re: Timing analysis - Peterson, James F (FL51)
[SI-LIST] Re: Pin Type Scope ground - Lee Ritchey
[SI-LIST] Re: Microstrip/Stripline - Ravinder . Ajmani
[SI-LIST] FW: Re: Microstrip/Stripline - Ray Anderson
[SI-LIST] Re: Microstrip/Stripline - Lee Ritchey
[SI-LIST] E1 EMI protection - Alex Horvath
[SI-LIST] Dielctric loss microstip/stripline - Babid A
[SI-LIST] Re: Dielctric loss microstip/stripline - Christopher.Jakubiec
[SI-LIST] Re: Dielctric loss microstip/stripline - Jian X. Zheng
[SI-LIST] Re: Microstrip/Stripline - Michael E. Vrbanac
[SI-LIST] Signal Integrity Job Opening - Brent Rogers
[SI-LIST] Re: Signal Integrity Job Opening - 韦竹林
[SI-LIST] IBIS Models for the Devices working at GHz speed - Darshan Mehta
[SI-LIST] Re: Microstrip/Stripline - Grasso, Charles
[SI-LIST] Re: Microstrip/Stripline - art_porter
[SI-LIST] Embedded Microstrip - Babid A
[SI-LIST] Re: Timing analysis - ariazi
[SI-LIST] Re: IBIS Models for the Devices working at GHz speed - Kai Keskinen
[SI-LIST] Re: Timing analysis - Kai Keskinen
[SI-LIST] how to evaluate the lead inductance of chip packages - david
[SI-LIST] Re: Microstrip/Stripline - Eric Bogatin
[SI-LIST] Question about termination of transmission line - Joey
[SI-LIST] Re: how to evaluate the lead inductance of chip packages - Lee Ritchey
[SI-LIST] Re: how to evaluate the lead inductance of chip packages - steve weir
[SI-LIST] Re: Question about termination of transmission line - Andrew Ingraham
[SI-LIST] Re: IBIS Models for the Devices working at GHz speed - Ken Willis
[SI-LIST] Re: Embedded Microstrip - Loyer, Jeff
[SI-LIST] sorting thru the junk mail - JaMi Smith
[SI-LIST] Happy Holidays - Dr. Edward P. Sayre
[SI-LIST] Re: Happy Holidays - Chris Cheng
[SI-LIST] Rs in W-element - TerenceHsieh
[SI-LIST] Re: Rs in W-element - Jinghua Huang
[SI-LIST] Re: sorting thru the junk mail - David Instone
[SI-LIST] Re: Happy Holidays - Dorin Oprea
[SI-LIST] Re: Rs in W-element - jan . vercammen1
[SI-LIST] Re: Rs in W-element - Muranyi, Arpad
[SI-LIST] Re: sorting thru the junk mail - Andrew Ingraham
[SI-LIST] Re: Happy Holidays - Andrew Ingraham
[SI-LIST] Calling subcircuits in HSpice - nrpatel
[SI-LIST] Re: Calling subcircuits in HSpice - Frank Dunlap
[SI-LIST] Re: Calling subcircuits in HSpice - Muranyi, Arpad
[SI-LIST] XAUI - Ravindra Johari
[SI-LIST] Re: Calling subcircuits in HSpice - nrpatel
[SI-LIST] Re: how to evaluate the lead inductance of chippackages - Lee Ritchey
[SI-LIST] Re: Calling subcircuits in HSpice - Lynne D. Green
[SI-LIST] Re: how to evaluate the lead inductance of chippackages - steve weir
[SI-LIST] Re: Calling subcircuits in HSpice - Andrew Ingraham
[SI-LIST] Re: sorting thru the junk mail - JaMi Smith
[SI-LIST] Re: sorting thru the junk mail - Ray Anderson
[SI-LIST] Re: Happy Holidays - Lee Ritchey
[SI-LIST] Re: XAUI - Lee Ritchey
[SI-LIST] Re: sorting thru the junk mail - JaMi Smith
[SI-LIST] Re: sorting thru the junk mail - Ray Anderson
[SI-LIST] Re: XAUI - Alex Horvath
[SI-LIST] Re: Copper atom density - JaMi Smith
[SI-LIST] Re: sorting thru the junk mail - JaMi Smith
[SI-LIST] Re: sorting thru the junk mail - Jacobson, Karl
[SI-LIST] Re: sorting thru the junk mail - Andrew Ingraham
[SI-LIST] Re: XAUI - steve weir
[SI-LIST] Re: XAUI - steve weir
[SI-LIST] Re: XAUI - Lee Ritchey
[SI-LIST] Re: XAUI - Cortex.Chen
[SI-LIST] Re: XAUI - steve weir
[SI-LIST] Hspice 2D EM Sim Vs. XFX 2D EM Sim - Guasti Giovanni
[SI-LIST] Hspice 2D Field Solver Vs. XFX - Guasti Giovanni
[SI-LIST] Re: Hspice 2D Field Solver Vs. XFX - Vijay Hosamani
[SI-LIST] Re: Hspice 2D Field Solver Vs. XFX - Scott McMorrow
[SI-LIST] Unsubscribe - Rich
[SI-LIST] Jon Powell - Lee Ritchey
[SI-LIST] Power Integrity- How to set Z target - Yosi Zanjiri
[SI-LIST] Re: Power Integrity- How to set Z target - z39453
[SI-LIST] IBIS models needed - Antselovitch Joseph
[SI-LIST] Re: IBIS models needed - Lynne D. Green
[SI-LIST] PCI-X 1.0a simulation - Naren Thesia
[SI-LIST] Re: PCI-X 1.0a simulation - steve weir
[SI-LIST] Re: PCI-X 1.0a simulation - Naren Thesia
[SI-LIST] Re: PCI-X 1.0a simulation - steve weir
[SI-LIST] Re: PCI-X 1.0a simulation - Andrew Ingraham
[SI-LIST] Re: IBIS models needed - Andrew Ingraham
[SI-LIST] Re: PCI-X 1.0a simulation - Aubrey_Sparkman
[SI-LIST] Re: PCI-X 1.0a simulation - Mcgrath, Christopher
[SI-LIST] Re: PCI-X 1.0a simulation - Scott McMorrow
[SI-LIST] Re: Hspice 2D Field Solver Vs. XFX - Loyer, Jeff
[SI-LIST] Re: FW: Re: Microstrip/Stripline - Loyer, Jeff
[SI-LIST] Taking SI and timing specs at face value - Dr. Edward P. Sayre
[SI-LIST] Re: Taking SI and timing specs at face value - steve weir
[SI-LIST] Re: PCI-X 1.0a simulation - Chris Cheng
[SI-LIST] Selection of Minimum Coupled Length in Cadence SPECCTRAQuest - Ravinder . Ajmani
[SI-LIST] Test DDR - Ravindra Johari
[SI-LIST] Re: Test DDR - Mehta, Darshan
[SI-LIST] Re: Test DDR - Scott McMorrow
[SI-LIST] Re: Test DDR - Hargin, Bill
[SI-LIST] Re: PCI-X 1.0a simulation - Aubrey_Sparkman
[SI-LIST] Re: Selection of Minimum Coupled Length in Cadence SPECCTRAQuest - Aubrey_Sparkman
[SI-LIST] Re: Selection of Minimum Coupled Length in Cadence SPECCTRAQuest - Ravinder . Ajmani
[SI-LIST] Re: PCI-X 1.0a simulation - Chris Cheng
[SI-LIST] Unsubscribe - 2nd attempt - Rich
[SI-LIST] Re: PCI-X 1.0a simulation - Aubrey_Sparkman
[SI-LIST] Re: PCI-X 1.0a simulation - Chris Cheng