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[SI-LIST] Re: Why is capacitor with high ESR

  • From: Chris Padilla <cpad@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 06 Dec 2004 11:02:10 -0800
Sorry for the ignorant question but I can't figure out what 'DET' 
is...allow yourself the smirk of visualizing me slapping myself in the 
forehead when you tell me.... :)

Thanks----->Chris

At 11:30 PM 12/5/2004 -0800, steve weir wrote:
>1.  Oscillator with nice fast CMOS drivers in the middle as our noise
>source, aside from local decoupling in the middle of the board, it will be
>an open cavity.
>2.  Same as 1. but with ground fence only at the board edges.
>3.  Same as 1. but with fence using DET with the best dissipative caps that
>we can get.
>4.  Same as 1, but with lots of ground  and power vias distributed around
>the board many connecting to decoupling caps on the surface.
>5.  Save as 4, but with fence as in 2.
>6.  Same as 4, but with DET as in 3.

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