FreeLists / si-list / [SI-LIST] Re: Signals crossing power plane split

[steve weir <weirsp@xxxxxxxxxx>]

Fabrizio,  the BC will help, but only so much.  If you cannot route around 
the breaks, then what you can do to mitigate the problem, is add decoupling 
between the various Vcc planes near the crossings.  Much beyond that, you 
are at the mercy of what the BC provides coupling down to ground and back 
up to the Vcc layer across the gap.

The limitation with discretes will be the induction loop in the decoupling 
network.  The energy will spread between the impedance of the BC, and the 
impedance of the discrete devices.  Consequently, if you must do this, do 
it for slow rise time signals.  If the driver is an FPGA I have a couple 
other things you can do.

Steve.

At 04:31 PM 12/3/2003 -0500, Fabrizio Zanella wrote:
>I have a few nets which are routed on a dual stripline layer, on a
>multilayer board, and these nets are referenced to ground on one side
>and a power plane with several split voltages on the other side. The
>signal layer, SIG LYR2, is 3 mils from the VCC plane and 8 mils from the
>ground plane.  The VCC plane is part of a BC layer, so it is 2 mils from
>a ground plane on the other side of the signals on SIG LYR2.  Both VCC
>and GND planes are 1.3 mils thick.
>
>       ____________________________________  GND LYR1
>                      ________       SIG LYR1
>GND LYR1 to VCC LYR = 11 mils
>
>                     _________      SIG LYR2
>SIG LYR2 to VCC LYR = 3 mils
>
>     ____________      gap     ________________VCC LYR        VCC LYR to
>GND LYR2 = 2 mils
>
>    _____________________________________  GND LYR2
>
>The nets in question, on SIG LYR2, have to cross gaps in the VCC layer.
>My question is, will the return current for these signals use GND LYR2
>as a reference to get across the splits?
>
>Thanks,
>
>Fabrizio Zanella
>Principal Hardware Design Engineer
>Broadbus Technologies
>fzanella@xxxxxxxxxxxx
>
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