Try this link it covers sequencing/ramping
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1133
Nico Fleurinck wrote:
> Dear all,
> For a virtex-II FPGA (XC2V2000) the power-on ramp must be minimum 1ms and
> maximum 50ms.
> Can anybody tell me how you can control the power on ramp of a certain
> voltage.
> Please let me know how you can do it.
>
> Best regards,
> Nico
>
> Nico Fleurinck
> Junior Design Engineer
> VERHAERT Satellites & Platforms
> Hogenakkerhoekstraat 21
> B-9150 Kruibeke
>
> Tel : +32 3 250.1984
> Fax : +32 3 254.1008
> e-mail : nico.fleurinck@xxxxxxxxxxxx
> Visit us : www.verhaert.com
>
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