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[SI-LIST] Re: 10 Layer Board Stack up

From: Mike Brown <bmgman@xxxxxxxxxx>
To: adeelm@xxxxxxxxxxx
Date: Tue, 03 Dec 2002 18:12:37 -0600
Adeel,

Your stackup seems workable.  I don't know what constraints you are 
working under, so I can't say whether there's something better.  It 
lacks closely-coupled power-ground plane pairs, so the power 
distribution might not be as quiet as you would like.

The thing to worry about on the split plane is impedance bumps and 
crosstalk where signals in the adjacent signal plane(s) cross over the 
split.  My preference for location is that place which minimizes the 
split crossings.  Liberal use of HF bypass caps on both sides of the 
split near the signal crossings will minimize the split-crossing 
problems.  This can be troublesome if there are a lot of splits, or a 
lot of signals crossing it/them.  Split planes can work, if you are careful.

You may need to be aware that the propagation velocity of  the outer 
layers is faster than the inner layers, if delay matching is part of 
your design requirement.  Simply equalizing the trace length is not 
enough, if the proportions on the outer and inner layers isn't the same. 
This is due to a portion of the field on the outer traces being in air, 
rather than confined to the board dielectric as in the inner layers.  It 
may or may not be an issue depending on the board timing design.

Regards

Mike

Adeel Malik wrote:

>Mike,
>     Can you recommend the stackup when the routing density dictates at
>least 6 signal layers?. I have employed successfully the following stackup
>for a 100MHz board:
> 1 TOP
> 2 GND
> 3 SIG1
> 4 PWR (corresponding to the mostly used Logic Supply Voltage by the digital
>circuits)
> 5 SIG2
> 6 SIG3
> 7 SPLIT POWER PLANE (Corresponding to the less frequently used supply
>voltages)
> 8 SIG4
> 9 GND
>10 BOTTOM
>
>While routing I keep the high-speed signals confined to Layer 1&3 or Layer
>8&10. Low speed signals having less stringent crosstalk requirements are
>confined to Layer 5&6. Can someone recommend me a better layout than the
>afore-mentioned one with 6 signal layers and 4 power planes ?
>Also I am curious to know what difference it makes by interchanging the
>order of Single Power Plane and Split Power Plane, i.e, interchanging Layer
>4 and Layer 7.
>
>ADEEL MALIK,
>Avaz Networks
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mike Brown
>Sent: Tuesday, December 03, 2002 7:20 AM
>To: nagaraj@xxxxxxxxxxxxxxxxxxxx
>Cc: vasudevan.duraiswamy@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: 10 Layer Board Stack up
>
>
>
>Nagaraj,
>
>Symmetry is important - so is shielding.  A modified stackup with cap
>(pad-only) layers top and bottom, with stripline construction, might be
>
> 1 pad
> 2 Gnd
> 3 Voltage
> 4 Sig
> 5 Gnd
> 6 Voltage
> 7 Sig
> 8 Gnd
> 9 Voltage
>10 Pad
>
>Given your voltage requirements, you could make layer 9 into a ground,
>but it would be beneficial to make it a voltage plane to lower the
>impedance on one of your voltages.  Or you could use it to distribute
>miscellaneous voltages.
>
>This construction gives you good shielding of the internal wiring, and a
>relatively constant impedance environment wherein you can switch layers
>to achieve routing with a minimum of impedance discontinuity. The
>stackup is immune to inter-layer crosstalk, and provides good HF
>decoupling of the power distribution system.  It also gives you room on
>the board surface to embed EC changes or to avoid seriously congested
>areas.  This use should be avoided if at all possible.
>
>Multiple ground (or power) planes are necessary because you have
>multiple signal layers and multiple voltage layers. Planes are needed
>adjacent to each signal layer to carry the return currents associated
>with fast risetimes.  Without the planes, the return currents find their
>way onto nearby wires and you become the victim of crosstalk.  If you
>have two signal lines between planes, they need to be routed at right
>angles to each other to minimize this problem. Ground planes are needed
>next to the voltage layers to provide low-impedance distribution of the
>voltages.
>
> Symmetry and shielding aren't everything.  There are probably thickness
>constraints dictated by the enclosure into which the board must plug,
>and by manufacturing component lead protrusion requirements.  There are
>6 dielectric layers (those between signal and adjacent plane) that must
>be relatively thick to give you a workable signal impedance, and 3
>(those between power and adjacent ground) that should be as thin as
>possible to provide low Z power distribution.
>
>I can't assess what this stackup would do to your manufacturability
>requirements.  I have used similar construction successfully, but the
>board thickness was always a nagging concern.
>
>Regards
>
>Mike
>
>Nagaraj wrote:
>
>  
>
>>Hi,
>>
>>We cann't Provide more GND Plane ( 4 ) as you specified and There is no
>>Provision for
>>
>>Splitting VCC2.5 in VCC3.3 Plane as There are 12V and 5 Volts are Already
>>Shared the VCC3.3 and 2.5 Plane
>>
>>Is there any Other Layer Stack up Can you Suggest.
>>
>>My Question is Why Multiple Ground are Very much Needed?
>>
>>
>>
>>Thanks in Advance
>>
>>Regards
>>
>>Nagaraj
>>
>>
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
>>vasudevan.duraiswamy@xxxxxxxxxxx
>>Sent: Monday, December 02, 2002 5:34 PM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: 10 Layer Board Stack up
>>
>>
>>
>>Hi,
>>
>>It is correct that the layers should be symmetrical, to provide better
>>copper balancing,
>>
>>Power planes are generally defined by
>>
>>     power integrity / decopling requirement
>>
>>     impedance requirement
>>
>>               Routability
>>
>>Your stack up can be modified as follows
>>
>>1)Top Signal 1
>>2)GND
>>3)Signal 2
>>4)VCC3.3
>>5)GND
>>6)VCC2.5
>>7)GND
>>8)Signal 3
>>9)GND
>>10)Bottom Signal 4
>>
>>
>>    Routing, switch  the signals between layer pair Top Signal 1 and
>>    
>>
>Signal
>  
>
>>2  or  between layer pair Bottom Signal 4 and Signal 3
>>
>>    Don't  switch over routing between  Signal 1/2  to Signal 3 / 4
>>
>>Incase of more routing layer requirement,  make layer 4 & 7 also routing
>>layer , make layer 5 split power plane of VCC 3.3 & 2.5, make layer 6 as
>>    
>>
>GND
>  
>
>>Regards,
>>
>>Vasudevan D
>>Technical Leader - PCB Design, CFT
>>Philips Software Centre Pvt Ltd,
>>Philips Innovation Campus,
>># 01, Murphy Road, Ulsoor,
>>Bangalore - 560 008. India
>>Tel: +91 80 5579 000 extn : 5030
>>fax : +91 80 5546 645
>>
>>
>>
>>                     stephanie.goedecke+FromInterNet@
>>                     philips.com                                  To:
>>si-list@xxxxxxxxxxxxx
>>                     Sent by:                                     cc:
>>(bcc: Vasudevan Duraiswamy/BTC/CFT/PHILIPS)
>>                     si-list-bounce@xxxxxxxxxxxxx                 Subject:
>>[SI-LIST] Re: 10 Layer Board Stack up
>>
>>
>>Classification:
>>                     2002-12-02 02:48 PM
>>                     Please respond to
>>                     stephanie.goedecke+FromInterNet
>>
>>
>>
>>
>>
>>
>>
>>Hi,
>>
>>generally, the layers should be symmetrical.  The details of the layout
>>depend on the
>>details of the board.
>>
>>Stephanie Goedecke
>>
>>Philips - SP3D Chip Design GmbH
>>Petersbrunnerstr.17
>>82319 Starnberg / Germany
>>
>>Phone:  +49-8151-270-160
>>Fax : +49-8151-270-200
>>
>>
>>
>>Hi ,
>>
>>In 10 Layer Board stack How Multiple Ground Plane Will be More effective
>>    
>>
>and
>  
>
>>Why.
>>
>>Is there any Formula/Thumb rule behind this.
>>
>>most of my Critical Signal ( CLK)  are Running at Signal Layer 1
>>and My Board Stack up is
>>
>>Top
>>GND
>>Signal Layer 1
>>VCC3.3
>>GND
>>VCC2.5
>>Signal Layer 2
>>Signal Layer 3
>>GND
>>Bottom
>>
>>
>>
>>Thanks in Advance.
>>
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>>    
>>
>
>
>
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>



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References:

[SI-LIST] Re: 10 Layer Board Stack up
From: Adeel Malik
[SI-LIST] Re: 10 Layer Board Stack up

Other related posts:
