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Thread Index for si-list, 12-2001

[si-list] || [12-2001 Date Index] [12-2001 Thread Index]

  1. [SI-LIST] Re: Buried Capacitance thread comments (The whole thing), Chris Cheng
  2. [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ), Ozgur Misman
  3. [SI-LIST] Re: lumped model vs distributed model, Abe Riazi
  4. [SI-LIST] AC Termination, Jim Hanson
  5. [SI-LIST] Re: Swing control for Gigabit chips, Alex March
  6. [SI-LIST] Re: AC Termination, Peterson, James F (FL51)
  7. [SI-LIST] Re: Square wave harmonics, Doug McKean
  8. [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing), Larry Smith
  9. [SI-LIST] Buried Capacitance & Low Inductance Packages, Harvey, Wilbur
  10. [SI-LIST] Re: Sanmina patent on dielectric thicknesses under 4 mi ls, Ritchey Lee
  11. [SI-LIST] 2.5D, Zhou, Xingling (Mick)
  12. [SI-LIST] Re: 2.5D, samir_aboulhouda
  13. [SI-LIST] Re: Buried Capacitance thread comments (The whole t hing), larry smith
  14. [SI-LIST] Virus Warning - Do Not Open e-mails with a subject line of "Hi" and "gone.scr" or "gone.zip" attachments!!!, Wang, Brian
  15. [SI-LIST] Ferrite Bead Models, Suresh Sivasubramaniam
  16. [SI-LIST] Re: Ferrite Bead Models, zanella, fabrizio
  17. [SI-LIST] PRBS Data patterns, Bob Patel
  18. [SI-LIST] PCI-X Specification!, Tariq Abou-Jeyab
  19. [SI-LIST] Re: PRBS Data patterns, Greim, Michael
  20. [SI-LIST] Re: PCI-X Specification!, Muranyi, Arpad
  21. [SI-LIST] 5 Gb/s Backplane Tranceiver Demo, Sainath Nimmagadda
  22. [SI-LIST] Slow-wave mode article, Sainath Nimmagadda
  23. [SI-LIST] Question on PLL for Data/Clock Recovery Apps, Rengarajan S Krishnan
  24. [SI-LIST] FW: SEEING IS BELIEVING! Accelerant Networks DEMO's 5Gb/s ! W, Greim, Michael
  25. [SI-LIST] Re: PCI-X Specification! - or meaning of overshoot?, Muranyi, Arpad
  26. [SI-LIST] Re: Undershoot, Overshoot, Zabinski, Patrick J.
  27. [SI-LIST] Re: transmission line model, Jason D Leung
  28. [SI-LIST] NCMS Report and Decoupling paper now available, Charles Grasso
  29. [SI-LIST] The Elusive Glitch - Part 3, Douglas C. Smith
  30. [SI-LIST] Re: NCMS Report and Decoupling paper now available, Kai Keskinen
  31. [SI-LIST] EMC Society contribution to SI, Charles Grasso
  32. [SI-LIST] Re: DDR SDRAM, Khederian, Bob
  33. [SI-LIST] Difficulties in opeining Embedded Decoupling pdf??, Charles Grasso
  34. [SI-LIST] Point to multi-point termination, Moore Mo(modaochun)
  35. [SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps, Ed Miguel
  36. [SI-LIST] Marty Jawitz, ashaughnessy
  37. [SI-LIST] Answering Protocol, Sainath Nimmagadda
  38. [SI-LIST] Re: Answering Protocol, bill
  39. [SI-LIST] Answering Protocol - Clarification, Sainath Nimmagadda
  40. [SI-LIST] PCI connector, =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
  41. [SI-LIST] cpu socket, =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
  42. [SI-LIST] Announcement for Photonic and Optoelectronic Packaging course at San Jose State University, Raj Raghuram
  43. [SI-LIST] RF System Design Seminars?, Girish Bangalore
  44. [SI-LIST] Re: RF System Design Seminars?, Rich Peyton
  45. [SI-LIST] Effects of flux on board performance, Ed Miguel
  46. [SI-LIST] IBIS, Khalid Ansari
  47. [SI-LIST] Re: IBIS, Kai Keskinen
  48. [SI-LIST] Re: PCI connector, Harvey, Wilbur
  49. [SI-LIST] Re: RMS jitter, Ingraham, Andrew
  50. [SI-LIST] Pls let me know., Inmyung Song
  51. [SI-LIST] Re: Pls let me know., Roy, Richard
  52. [SI-LIST] OPENING: Juniper Networks: Signal Integrity Engineer, Heinz Blennemann
  53. [SI-LIST] ESD protection, Mike Devita
  54. [SI-LIST] Re: ESD protection, Volk, Andrew M
  55. [SI-LIST] Resistor noise specs, Melenhorst, Mathieu
  56. [SI-LIST] [Fwd: Resistor noise specs], Paul Levin
  57. [SI-LIST] Cin in IBIS models, Bob Patel
  58. [SI-LIST] Re: Cin in IBIS models, Muranyi, Arpad
  59. [SI-LIST] Re: Marty Jawitz, Bremer, Bob
  60. [SI-LIST] Differential Pair, =?big5?b?Um9nZXIuV3UgKKdkrVqqTCk=?=
  61. [SI-LIST] Looking for SI position in Ottawa, Canada, Hassan O. Ali
  62. [SI-LIST] Seminars & Books - Signal Integrity Design, Craciun, Liviu-Dumitru
  63. [SI-LIST] Solder Mask, Zhou, Xingling (Mick)
  64. [SI-LIST] Software questions, Shiming Wang
  65. [SI-LIST] 10 BASE-T RJ45 PCB Design information, Peter Baxter
  66. [SI-LIST] 100Base-T signalling, Bob Patel
  67. [SI-LIST] s2ibis2 conversion, Ravikumar Chirugudu
  68. [SI-LIST] Reflection and EMI, chlee99
  69. [SI-LIST] AW: Re: AW: Effects of flux on board performance, Thomas Beneken
  70. [SI-LIST] Re: selection of Tx line models depending on frequency, Degerstrom, Michael J.
  71. [SI-LIST] selection of Tx line models depending on frequency, Lynne Green
  72. [SI-LIST] eye diagram, bharatkumarbhat
  73. [SI-LIST] Re: eye diagram, Zhou, Xingling (Mick)
  74. [SI-LIST] Re: Hairpin?, Ray Anderson
  75. [SI-LIST] Hspice simulation for SI, cheart
  76. [SI-LIST] Re: Hspice simulation for SI, cheart
  77. [SI-LIST] question LINPAR tool, jan . vercammen . jv1
  78. [SI-LIST] Re: 10 BASE-T RJ45 PCB Design information, Peterson, George W
  79. [SI-LIST] PECL Tree structure, Ashok Babu K
  80. [SI-LIST] LVPECL -to-LVDS translator, s.raja
  81. [SI-LIST] Re: PECL Tree structure, Ingraham, Andrew
  82. [SI-LIST] Burried capacitor and resistor design, BRIGHT ZHOU
  83. [SI-LIST] SI Engineer Qualification, Lum Wee Mei
  84. [SI-LIST] SA12E Vil and Vih, mike
  85. [SI-LIST] A question about PCI bus termination., Moore Mo(modaochun)
  86. [SI-LIST] Re: A question about PCI bus termination., Ingraham, Andrew
  87. [SI-LIST] Equation, Rich Peyton




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