[SI-LIST] Re: Buried Capacitance thread comments (The whole thing)
From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Sat, 1 Dec 2001 15:45:31 -0800
Mike,
You are being to annoy me. You are running around saying in
general terms what to do in PCB design but you have yet to
explain a single reason why the above 200MHz decoupling is
needed by using a Zycon plane in a PCB. You are throwing
in terms like split planes and switching supplies none of
which has anything to do with needing a Zycon plane. The former
has to be managed by the planar capacitance sandwiching the
signal traces(case 1b in my previous discussion)nothing you
can do with Zycon planes. In the later case, I've never heard
of 200MHz noise or even less than uf decoupling caps are
needed for switch regulators.
You continue to hide behind other people's paper to
justified your claim. Ever wonder why those authors from
that company didn't jump up to defend you or attack me ?
(Well, actually one of them try to subtly agree with me.)
Because they know my old group in that company pioneered most
of the packaging and electrical analysis in that company.
Some of them started those analysis under the guidance of
my old group. I designed most of the original CPU packages
and did most of the electrical analysis myself. I designed
every single server processor modules in that company until
I left and you better believe I know what are the package
resonance and electrical characteristics of the things
they designed. Like I said, BTDT. I am still in very good
terms with their seniors and for sure I don't want/need
to pull ranks in a technical discussion.
You are so proud of your experiences in designing above GHz
systems. I suggest you go get an NDA and take a look at
those high power high frequency CPU platform design guides.
Take a look at their power distribution guideline and
you will know everything I said about not needing system
decoupling above 200MHz is correct and you are totally
out of line. Why do I know that ? Because I managed one of
the first group in that PC chip company to performance these
type of power distribution analysis and electrical
characterization. It will be unfair advantage to me to
quote the public domain design guide on their PC platform
power distribution guideline because they are using
sockets. However, their highend high power processors
has a much more complicated but relative low impedance
power pod connector. Even under those condition, NO
NEED FOR ABOVE 200MHz DECOUPLING.
Your reference to needing Zycon planes for decoupling
core noise above 200MHz makes as much sense as trying
to sell me a super soaker because there is a fire in
a building down a block. No thanks, I will take a fire
truck and park next to that building and turn on the
fire hose.
You continue to quote the Zycon paper on justifying
their use. I have already pointed out the fundamental
flaw in that experiment (lack of return current path
necessitate the Zycon planes). I told you I used Zycon
before and I didn't see any different in real world
power distribution improvement. What I didn't say
was I was presented the same paper you mentioned and
I specifically pointed out that flaw and the
presenter has no choice BUT TO AGREE WITH WHAT I SAID.
It doesn't matter how many years you have worked in
this industry or how many designs you have done. Some
of the engineers who worked for me are fresh out of
grad school doing their first design. Yet they have
learned through their work and demonstrated a better
understanding in electrical design and analysis
than you.
-----Original Message-----
From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
Sent: Friday, November 30, 2001 10:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Buried Capacitance thread comments (The whole
thing)
Scott presents a good summary of a portion of the questions raised on this
thread by his comment below. This guidance is probably the most important
one
to SI engineers.
"Chris has provided some additional excellent clarifications which
I am generally in agreement with. The point that he (we) make
is that if you engineer your return paths from die to die, the amount
of noise which you have to contain through decoupling, thin
dielectrics and extraordinary EMI control techniques is reduced
drastically."
However, other design areas impact the overall EMC performance of a design
and must be integrated with the above. These include items noted by Chris
such as beneficial planar stitching and the impact of myriads of vias.
Additionally, there are planar splits (both power and ground), EMI
confinement of on-board switching supplies (which are now often operating at
1 MHz or above), and a number of other special considerations that each
different design seems to bring up. Most of these items have been discussed
previously in the SI List forum.
One of the most prominent solutions to these other EMC problems is the use
of
excellent planar bypassing/decoupling, which has been covered in-depth by
many (especially by our distinguished colleagues at Sun Microsystems; i.e.,
Larry, Ray, and Istvan). Local and board-wide capacitor decoupling is the
mainstay for lower frequency disturbances, but is limited (by inductance
from
physical construction and the length of connections to the planes) to under
200 MHz. That's where the interplanar capacitance, which inherently exhibits
minimal inductance, takes over. The thinner the dielectric between the
planes
to be decoupled, the better the decoupling. This rationale was the stimulus
for my earlier comments and was meant to assure our less educated colleagues
were not misled as to the "simplicity" of achieving EMC in a design. A
complex, high-density design requires implementation of all the techniques
at
our disposal.
I apologize for any interpretation that I was personally attacking Chris in
my initial comments. I was stating a heated difference of opinion on a
subject I helped pioneer in the area of high-speed digital design. I'm glad
Chris responded in depth to Scott's initial comments, as he has a lot to
offer the forum. For the record, I only accept approximately one in five
consulting requests that I perceive are the most challenging/difficult. All
requests for my consulting services are by word-of-mouth recommendations as
I
do not advertise; i.e., there are no "scare tactics" in my portfolio. I have
directly designed or guided over 1000 complex PCB designs in the last 16
years of consulting for an average exceeding 20 different clients per year.
My client repeat rate is >98%. In the last two years, I have not worked on
an
active board that did not have some portion of the circuit(s) operating in
excess of 1 GBPS (most above 2 GBPS), and not one of them had under 2000
vias. I critique and guide from one to five board designs per client. (How
many boards does a corporate employee see each year?) My EMC modeling,
analysis, and design techniques have achieved performance on (classified)
programs that is over 60 dB (yes 60) below FCC Class B levels. Hopefully,
this background experience constitutes enough "real world" evidence so no
one
thinks I am purely academic.
Good engineering to all of you.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
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