FreeLists / si-list / [SI-LIST] Buffer delay

[yan hang <yang@xxxxxxxxxx>]

Hi All,
           Now I do some board timing simulations .  I got the hspice =
model
and ibis model for same buffer. Then I set a test fixture(Ex.
Cref=3D15pf,Rref=3D1E6,Vref=3D3.3V),I contrast the simulation result of =
buffer
dealy using hspice model and ibis model. I found there is a little big
diffrence between them.
           So when translate hspice model to ibis model,how to consider
about the buffer deley issue? =20
           Should I trust the buffer delay value from ibis model =
simulation?

Best Regards.

Yan Hang
Huawei Technology
086-21=A3=AD68644808=A3=AD24043


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