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[SI-LIST] ddr2 2 sodimm design - clk to add&control signals metcing

From: "Moshe Frid" <moshef@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 15 Nov 2006 11:52:20 +0200

 
 

________________________________

 

 

Hello all

 

My question is about length matching between diff clk signals and
address & control signals in 2 sodimm system 

 

That connected in 128 bit ddr2 bus

 

What should be the rule of that length

 

Do I need to match the clk also to the data bytes  

 

Thanks

________________________________

Moshe Frid 

 

 


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