FreeLists / si-list / [SI-LIST] Copper pours on a 2-layer PCB

["Carlos Toro" <torocar@xxxxxxxxx>]

Hello you all. Unfortunelly, the local company which we pretend to hire for
manufacturing our board just makes 2 layer boards (max). Probably our design
wouldn't require more than that but since it is our the first time we
pretend to hire the services of such a company some doubts have come up.
The PCB engineers have assigned both the TOP and BOTTOM layers as routing
layers (not plane layers, since there are only two layers to work on). The
TOP layer is being used for routing as many signals and +5V power traces as
possible while in the BOTTOM layer a copper pour attached to GND is to be
placed (there are some spots where signal traces partially go in the BOTTOM
layer since sometimes they cross, however, one of the goals is to chop the
BOTTOM layer as less as possible). The PCB is basically a development board
prototype for a microcontroller. There are not high power components
involved.
*Now, these are the doubts that have come up through the layout process and
I would like you to kindly give me your advice on:*
**
*1. Should a copper pour attached to +5V be placed in the TOP layer?. An
effort has been put on for distributing both power and GND in a star shape
fashion (in order to avoid impedance coupling between ICs). But I'm afraid
that If a +5V copper pour is placed in the TOP layer the star
POWER/GND distribution topology will be lost (since the pour will bond to
the +5V traces because it is electrically the same net). Should the copper
pour respect the star topology +5V traces ?*
**
*2. Should the copper pour of the TOP layer be attached to the GND net
instead?*
**
*3. A star topology has been used for placing the GND supply traces (trying
to locate them underneath +5V traces). If a copper pour is placed in the
BOTTOM layer attached to GND, the star topology will be lost (for the same
reason as topic # 1). Acording to the theory, the returning current of all
the signal traces and power traces will try to go come back right under the
respective trace providing there is a GND return trace or plane underneath
(that is, the returning current always seeks for the **least impedance
path). If +5V (TOP layer) is distributed in a star fashioned way, the
physics would take care of the rest, right? (I mean even if the bottom layer
has a GND copper pour eating up the star topology GND traces, the "mirror
effect" would "copy" the star topology from the TOP layer to BOTTOM?).
Should the copper pour respect the star topology GND traces ?*
**
I would REALLY appreaciate if you kindly could provide some advices about
these matters.

THANK YOU SO MUCH BEFOREHAND.

-- 
Carlos Toro B
Design Engineer
JAVERIANA STEREO
Calle 18 No. 118-250
Cali, Colombia
South America

Office Phone: +57 2 2725032
Mobile Phone: +57 315 474 5872


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