Date Index for si-list, 11-2006

[si-list] || [11-2006 Date Index] [11-2006 Thread Index]

[SI-LIST] Electrical Design of Advanced Packaging and Systems (EDAPS) - Madhavan Swaminathan
[SI-LIST] Electrical Design of Advanced Packaging and Systems (EDAPS) - Madhavan Swaminathan
[SI-LIST] flip chip model for DDR3 - Nidhir Kumar
[SI-LIST] Leading Insight Northwest - Ansoft Application Workship - Nov. 14 in Beaverton, OR - Andrew Byers
[SI-LIST] DDR Interface Topology - Bingipur, Arjun
[SI-LIST] Re: DDR Interface Topology - steve weir
[SI-LIST] one problem about ESD simulation - chenglubeijing
[SI-LIST] How to simulate ESD test of one chip CMOS chip - ChrisCheng
[SI-LIST] Signal Integrity Position - Andover MA - Haller, Robert
[SI-LIST] A question for the instrument guys on TDR and TDT - Chris Cheng
[SI-LIST] AMD Hiring SI Engineer - jworth
[SI-LIST] Re: DDR Interface Topology - Kai Keskinen
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Istvan Novak
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Chris Cheng
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Istvan Novak
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Chris Cheng
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Istvan Novak
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - steve weir
[SI-LIST] Hi - janani
[SI-LIST] hai test mail - Abin.CV
[SI-LIST] SSO corner cases - Canes Venatici
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Chris Cheng
[SI-LIST] TEST MAIL - Girish gopi
[SI-LIST] Re: Heatsink electrical isolation - Hill, John
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Scott McMorrow
[SI-LIST] Re: How to simulate ESD test of one chip CMOS chip - Grasso, Charles
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - dmitry.a.smolyansky
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - steve weir
[SI-LIST] Re: DDR Interface Topology - Todd Westerhoff
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Chris Cheng
[SI-LIST] Signal and Power Integrity Applications Engineer Vacancy - marcekowalski
[SI-LIST] User2User 2007 Call4Papers ... - Hargin, Bill
[SI-LIST] Board/DVT project in San Jose, CA - Kevin Pierpoint
[SI-LIST] Short-term Consulting - Jory McKinley
[SI-LIST] How to evaluate IBIS model - Zhangkun
[SI-LIST] Re: How to evaluate IBIS model - Muranyi, Arpad
[SI-LIST] Re: How to evaluate IBIS model - Lynne D. Green
[SI-LIST] RF shapes behaviour at high speeds - chand basha
[SI-LIST] unsubscribe - Vigneshwara Upadhyaya
[SI-LIST] Conductor loss or Dielectric loss - hkkim
[SI-LIST] Re: Conductor loss or Dielectric loss - Saoer Sinaga
[SI-LIST] Trace length problem - lijingdea
[SI-LIST] Hi Test - Partha Simon
[SI-LIST] Re: Trace length problem - Muranyi, Arpad
[SI-LIST] Job opening: Signal Integrity Engineer - Tanmoy Roy
[SI-LIST] Re: Conductor loss or Dielectric loss - Andrew Byers
[SI-LIST] Re: Conductor loss or Dielectric loss - Abe (Abbas) Riazi
[SI-LIST] Re: Conductor loss or Dielectric loss - Kai Keskinen
[SI-LIST] Re: Conductor loss or Dielectric loss - hkkim
[SI-LIST] Copper pours on a 2-layer PCB - Carlos Toro
[SI-LIST] Novel chip-to-chip interconnect hits 10 Gbit/s - rbmerrit
[SI-LIST] Package SI - Madhusudhan Kulkarni
[SI-LIST] Re: Copper pours on a 2-layer PCB - Jack Olson
[SI-LIST] Re: Copper pours on a 2-layer PCB - David Lieby
[SI-LIST] Fwd: Re: Copper pours on a 2-layer PCB - Carlos Toro
[SI-LIST] Re: Fwd: Re: Copper pours on a 2-layer PCB - Carlos Toro
[SI-LIST] EMI/EMC Seminar - Surendra
[SI-LIST] EMC engineer position open in Shanghai, China - Howard Ji \(howardji\)
[SI-LIST] Recall: EMC engineer position open in Shanghai, China - Howard Ji \(howardji\)
[SI-LIST] COMMANDS - Richard Kroposki
[SI-LIST] UNSUBSCRIBE - Richard Kroposki
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - dgun
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Chris Cheng
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - dmitry.a.smolyansky
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Craig Twardy
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - Tom Dagostino
[SI-LIST] Series resistor b/w grounds - nagaraj
[SI-LIST] How to generate IBIS model - Gang Sun
[SI-LIST] Re: Package SI - Sureshbabu
[SI-LIST] Fiber transceiver assemblies, fully assembled? - Steven Kan
[SI-LIST] ddr2 2 sodimm design - clk to add&control signals metcing - Moshe Frid
[SI-LIST] Re: How to generate IBIS model - Abdulrahman Rafiq -X \(arafiq - Digital-X, Inc. at Cisco\)
[SI-LIST] Re: Fiber transceiver assemblies, fully assembled? - Kai Keskinen
[SI-LIST] immediate opening for Board Design Lead - Josh Nickel
[SI-LIST] Re: A question for the instrument guys on TDR and TDT - dgun
[SI-LIST] Buffer delay - yan hang
[SI-LIST] Re: Buffer delay - raj singh
[SI-LIST] Re: Fiber transceiver assemblies, fully assembled? - Ecklund, Tim
[SI-LIST] Re: immediate opening for Board Design Lead - Josh Nickel
[SI-LIST] Re: Buffer delay - Mirmak, Michael
[SI-LIST] Re: Buffer delay - Lynne D. Green
[SI-LIST] noise/emi getting into signal measurements - Doug Smith
[SI-LIST] About S2ibis2 - james cui
[SI-LIST] Re: Buffer delay - yan hang
[SI-LIST] Re: Buffer delay - Lynne D. Green
[SI-LIST] Re: About S2ibis2 - Lynne D. Green
[SI-LIST] Thick vs. thin diff. pairs - Mark Burford
[SI-LIST] Re: Thick vs. thin diff. pairs - David Instone
[SI-LIST] Re: Thick vs. thin diff. pairs - Ravinder . Ajmani
[SI-LIST] Re: Thick vs. thin diff. pairs - Christopher McGrath
[SI-LIST] Re: Thick vs. thin diff. pairs - Scott McMorrow
[SI-LIST] Re: Thick vs. thin diff. pairs - Loyer, Jeff
[SI-LIST] Re: Thick vs. thin diff. pairs - Christopher McGrath
[SI-LIST] Re: Buffer delay - zheng qi
[SI-LIST] Re: Buffer delay - Tony Luan
[SI-LIST] Re: Buffer delay - zhangkun 29902
[SI-LIST] Re: Buffer delay - YAK LHASA
[SI-LIST] Re: Thick vs. thin diff. pairs - Mark Burford
[SI-LIST] Trace impedance - shekhar sharma
[SI-LIST] Re: Buffer delay - David Lieby
[SI-LIST] Re: Trace impedance - David Instone
[SI-LIST] 回复:Statistical Timing Budgets Analysis - zhangkun 29902
[SI-LIST] Re: Trace impedance - Doug Brooks
[SI-LIST] Statistical Timing Budgets Analysis - wad
[SI-LIST] Re: Trace impedance - Doug Brooks
[SI-LIST] Re: Buffer delay - Muranyi, Arpad
[SI-LIST] Re: Buffer delay - Moran, Brian P
[SI-LIST] SI job posting, Celestica, Ottawa ON - Kai Keskinen
[SI-LIST] Re: Thick vs. thin diff. pairs - bratfest
[SI-LIST] Re: Trace impedance - David Instone
[SI-LIST] Why no timing model available unitl now? - Peter Zhu (Zhu Yonghui)
[SI-LIST] Re: Statistical Timing Budgets Analysis - Craig Twardy
[SI-LIST] Re: Trace impedance - Doug Brooks
[SI-LIST] Re: Why no timing model available unitl now? - Tom Biggs
[SI-LIST] Re: Trace impedance - Grasso, Charles
[SI-LIST] A New Open Source SI Analysis Tool - Charles Eidsness
[SI-LIST] Re: A New Open Source SI Analysis Tool - Yaron Kretchmer
[SI-LIST] Re: A New Open Source SI Analysis Tool - Charles Eidsness
[SI-LIST] Re: Trace impedance - thomas_beneken
[SI-LIST] Differential IBIS model (with pre-emphasis) generation - david horan
[SI-LIST] Trace width for 20 amps - RameshK Cozerv IN HO
[SI-LIST] Re: Trace width for 20 amps - Luc Durand
[SI-LIST] PICMG3.1 : is length matching really necessary? - Daniel . Peron
[SI-LIST] Re: Thick vs. thin diff. pairs - Lee Ritchey
[SI-LIST] Slew Rate Calculation - Bingipur, Arjun
[SI-LIST] Test Mail Please Ignore - ChandraKanth Gajawada
[SI-LIST] Re: Thick vs. thin diff. pairs - Istvan Novak
[SI-LIST] Re: Thick vs. thin diff. pairs - Mark Burford
[SI-LIST] Re: Thick vs. thin diff. pairs - Istvan Novak
[SI-LIST] Re: Slew Rate Calculation - Benny Yan
[SI-LIST] ESD simulations - Canes Venatici
[SI-LIST] hspi new release - Ke Wang
[SI-LIST] Re: hspi new release - Ke Wang
[SI-LIST] si-list web site address change - Ray Anderson
[SI-LIST] Re: ESD simulations - Yafei Bi
[SI-LIST] About S2ibis2 - james cui
[SI-LIST] Re: About S2ibis2 - Lynne D. Green
[SI-LIST] Re: About S2ibis2 - james cui
[SI-LIST] Patents on backplane, via design, misc... - Bill Dempsey
[SI-LIST] Re: ESD simulations - Srivats Partha
[SI-LIST] Re: ESD simulations - Canes Venatici
[SI-LIST] Re: PICMG3.1 : is length matching really necessary? - Daniel . Peron
[SI-LIST] digital core model - Saoer Sinaga
[SI-LIST] Re: ESD simulations - Adeel AHMAD
[SI-LIST] R: digital core model - gianguida
[SI-LIST] Re: R: digital core model - Saoer Sinaga
[SI-LIST] R: Re: R: digital core model - gianguida
[SI-LIST] Re: R: Re: R: digital core model - Saoer Sinaga
[SI-LIST] Re: ESD simulations - Yafei Bi
[SI-LIST] Re: R: Re: R: digital core model - Yafei Bi
[SI-LIST] Re: Slew Rate Calculation - Bingipur, Arjun
[SI-LIST] Re: Slew Rate Calculation - Tom Dagostino
[SI-LIST] Re: Slew Rate Calculation - Cortex.Chen
[SI-LIST] Re: Slew Rate Calculation - tao xu
[SI-LIST] Re: Slew Rate Calculation - Bingipur, Arjun
[SI-LIST] Re: Slew Rate Calculation - Bingipur, Arjun
[SI-LIST] Re: Slew Rate Calculation - tao xu
[SI-LIST] Re: Slew Rate Calculation - Bingipur, Arjun
[SI-LIST] trace length matching - p_pornchai
[SI-LIST] use of PVT corner models for various speed-grades - Zabinski, Patrick
[SI-LIST] Re: trace length matching - syedmhusain
[SI-LIST] Re: trace length matching - Jory McKinley
[SI-LIST] Electrical Engineering Manger - bruce harvie
[SI-LIST] Package signal integrity position at NXP - Chris Wyland
[SI-LIST] DDR2 IMPEDANCE - Kenny Frohlich
[SI-LIST] Re: DDR2 IMPEDANCE - Jory McKinley