FreeLists / si-list / [SI-LIST] Re: DDR SDRAM signal routing

["Tom Biggs" <tbiggs@xxxxxxxxxxxxxxxxxxxxx>]

See if I can summarize some points that people are saying (not everyone
agrees with #2):
1. Appnotes, evaluation board schematics are probably not sufficient to
design a reliable DDR interface.
2. If the vendor has gone out if its way to run extensive simulations
and built and tested hardware, and they have published well written
design rules, and you trust them, and your design matches theirs
exactly, you can probably design it without simulations.
3. Doing anything else requires lots of prayer and luck.=20

So to answer Peter Miller's original question, convince your boss that
you'll probably save money and time in the long run if you are allowed
to do simulations (you stated that this wasn't an option). If you can't
convince him/her, you could try contacting AMCC to see if they have #2
above. Otherwise you are stuck at #3.

Good luck!

    -tom



-----Original Message-----
From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx]=20
Sent: Tuesday, November 09, 2004 5:09 PM
To: scott@xxxxxxxxxxxxx; weirsp@xxxxxxxxxx
Cc: Tom Biggs; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR SDRAM signal routing


Couldn't agree more with Scott.
We had a product designed round a app note that
insisted on 15mil width traces and a 5mil plane
separation for clocks. Well you can just imagine the SI issues!! Can you
say "step on the leading edge"?

Chas



On Tue, 09 Nov 2004 00:44:29 -0500, Scott McMorrow <scott@xxxxxxxxxxxxx>

wrote:

> I'd second what Steve says.  In my experience, just because an=20
> application note says it's so, don't make it so.  The problem with the

> simulations (and app notes) of others are those pesky little unstated=20
> assumptions.  Sometimes they are unstated yet still considered in the=20
> analysis.  Sometimes they are unstated and were not considered.  And=20
> other times they are unstated and what was considered is just plain=20
> wrong.  Few if any application notes and design guides explicitly=20
> state all the assumptions used.  In fact, many of the assumptions are=20
> considered proprietary by semiconductor companies.  (When was the last

> time you performed an analysis on a processor bus and included the=20
> tester guard band for the processor and the controllerin your timing
> analysis?)
>
> The bottom line:  If you want explicit control over all assumptions in

> your system (and therefore want to take responsibility for engineering

> of that system) then you will roll your own simulations and perform=20
> your own analysis .... or suffer the consequence.  Unless, of course,=20
> you can get a semiconductor to certify that their application notes or

> design guidelines are error free.
>
> Y'all might want to take some time and read the legal disclaimers. =20
> They are there for a reason.
>
> regards and happy simulating,
>
> scott
>



--=20
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