FreeLists / si-list / [SI-LIST] Re: DDR SDRAM signal routing

["Charles Grasso" <cgrassosprint1@xxxxxxxxxxxxx>]

Couldn't agree more with Scott.
We had a product designed round a app note that
insisted on 15mil width traces and a 5mil plane
separation for clocks. Well you can just imagine the SI issues!!
Can you say "step on the leading edge"?

Chas



On Tue, 09 Nov 2004 00:44:29 -0500, Scott McMorrow <scott@xxxxxxxxxxxxx>  
wrote:

> I'd second what Steve says.  In my experience, just because an
> application note says it's so, don't make it so.  The problem with the
> simulations (and app notes) of others are those pesky little unstated
> assumptions.  Sometimes they are unstated yet still considered in the
> analysis.  Sometimes they are unstated and were not considered.  And
> other times they are unstated and what was considered is just plain
> wrong.  Few if any application notes and design guides explicitly state
> all the assumptions used.  In fact, many of the assumptions are
> considered proprietary by semiconductor companies.  (When was the last
> time you performed an analysis on a processor bus and included the
> tester guard band for the processor and the controllerin your timing
> analysis?)
>
> The bottom line:  If you want explicit control over all assumptions in
> your system (and therefore want to take responsibility for engineering
> of that system) then you will roll your own simulations and perform your
> own analysis .... or suffer the consequence.  Unless, of course, you can
> get a semiconductor to certify that their application notes or design
> guidelines are error free.
>
> Y'all might want to take some time and read the legal disclaimers.  They
> are there for a reason.
>
> regards and happy simulating,
>
> scott
>



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