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[SI-LIST] Re: DDR SDRAM signal routing
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Tue, 9 Nov 2004 10:52:13 -0800
Hi Scott,
I don't want this to turn into a dialogue on Intel, so I'll cut it
short. I'm just a poor but honest SIE enginner and
can't speak to Intel policy. I will say, however, that our mandate in
SIE is that we do not
publish any guidelines that are not 100% verified with both simulation
as well as extensive hardware
validation. So you can have high confidence in them. Application notes
are considered slightly less sacred,
and in some cases provide stand alone analytical analysis or share
technical expertise and recommendation, but are
not neccessarily verified with both simulation and hardware validation.
The disclaimers on application notes
are a bit more robust and should be read carefully.
Brian P. Moran
Senior SIE Engineer
Intel Corporation
brian.p.moran@xxxxxxxxx
________________________________
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Tuesday, November 09, 2004 10:23 AM
To: Moran, Brian P
Cc: Dan Bostan; leeritchey@xxxxxxxxxxxxx; Tom Biggs;
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR SDRAM signal routing
Brian
So based on your comments, I understand that Intel Corporation will
Guarantee the design solutions that are provided to customers in
application notes and design guidelines. Is that correct?
scott
Moran, Brian P wrote:
Hi Dan,
Your point is well taken. If you're willing to do the
simulations you
can sometimes further optimize the design for your specific
solution
space, and in some cases perhaps even eliminate the need for
some
components. For example, series Rs are often specified in
guidelines to
cover certain topology corner cases that do not exist in some
designs,
but do exist within the overall solution space simulated in the
generation
of the guidelines. So if you have the time and resources there
is always
potential to leverage your knowledge of the actual platform
design and
stackup to further optimize. Another example would be the PCB
fabrication parameters. Our guidelines assume a fairly wide
range of
material tolerances and trace tolerances. These ranges are
specifed to
cover 90% of the known PCB vendor space, so customers can use
the most
cost effective vendors. If you know your using a higher tier
vendor with
tighter capabilities, you can ring more out of your design that
our
guidelines might specify. It's a question of return on
investment, but I
would never discourage anyone from doing their own simulation,
especially where a design is known to have fewer degrees of
freedom than
the general case. Before I start removing components, however,
I'd want
to have complete confidence in my models. The good news is you
don't
have to simulate if you can live with the generic solution.
=20
Brian P. Moran=20
Calistoga SIE Kit Leader=20
Intel Corporation=20
brian.p.moran@xxxxxxxxx=20
-----Original Message-----
From: Dan Bostan [mailto:dbostan@xxxxxxxxx]=20
Sent: Tuesday, November 09, 2004 9:46 AM
To: Moran, Brian P; leeritchey@xxxxxxxxxxxxx; Tom Biggs;
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR SDRAM signal routing
I beg to differ with Brian, because I just simulated such an
interface
and was able to eliminate a couple of components and improve the
quality
at the same time.
I would say that the simulation of a DRR interface is mandatory.
/dan
--- "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
<mailto:brian.p.moran@xxxxxxxxx> wrote:
Hi Folks,
=20
As frequency bins move upward you find new sources of SI
issues even=20
in legacy DDR2/3 topologies. This along with subtle
changes in buffer=20
designs and SDRAM module design require extensive
frequency domain and
time domain simulations be done for every new DDR2/3
generation.
Fortunately, the mainstream memory controller vendors do
all of this=20
for the end users and provide guidelines which if
followed allow the=20
associated platform designs to be launched successfully
without=20
simulation. A lot of analysis also goes into the JEDEC
raw card=20
specifications to ensure the resident portion of the
topologies are=20
optimized. So in most cases the end user does not need
to simulate.=20
Just follow the guidelines.=3D20
=20
Intel provides such guidelines and only recommends
simulation when the
design deviates from our assumptions in terms of
platform stackup, bus
lengths, and/or routing geometries. We try to provide a
guaranteed=20
solution space which is adequate to allow our customers
to build their
full line of boxes and get to market without extensive
amounts of=20
simulation. Of course most big system houses have
simulation resources
and expertise, but its not necessarily required unless
the design is=20
unique in some way. Where simulation is needed is for
people doing=20
non-standard applications using non-PC form factors
and/or memory down
on the motherboard, etc... Another can of worms applies
to folks using
dual stripline stackups where layer to layer coupling is
not zero, or=20
where pure orthogonal routing rules can generate higher
than expected=20
via counts. In these cases auxiliary simulation should
be performed.=20
=3D20
=20
=20
=20
Brian P. Moran=3D20
Calistoga SIE Kit Leader=3D20
Intel Corporation=3D20
brian.p.moran@xxxxxxxxx=3D20
=20
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Monday, November 08, 2004 10:33 AM
To: Tom Biggs; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR SDRAM signal routing
=20
All you have to do then, is trust those simulations.
Based on the
accuracy of the average application note, is that a good
thing to do?
=20
Lee W. Ritchey
Speeding Edge
P. O. Box 2194
Glen Ellen, CA 95442
Phone- 707-568-3983
FAX- 707-568-3504
=20
I just used the energy it took to be angry to write some
blues.
Count Basie
=20
=20
[Original Message]
From: Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
<mailto:tbiggs@xxxxxxxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
<mailto:si-list@xxxxxxxxxxxxx>
Date: 11/8/2004 10:14:43 AM
Subject: [SI-LIST] Re: DDR SDRAM signal routing
I'm going to play devil's advocate here just to
get people thinking.
(Note that I simulate the DDR designs I've
done).
Ed says "The driving force behind all this is
time
to market and=3D20
system reliability."
There is one other force: cost. These days we
can
be easily outsourced
=20
if we are too expensive to our bosses.=3D3D20
How many IBM PowerPC 440GX (now AMCC's chip)
designs have been done?=3D20
How many times have people simulated them and
come
up with design=3D20
guidelines that will work? Yes, many of these
designs are different=3D20
from each other, but I would bet that many of
them
are EXACTLY the=3D20
same. Do we need 100 engineers to simulate the
exact same thing 100=3D20
times to come up with 100 identical sets of
routing rules?=3D3D20
If AMCC ran lots of simulations, then came out
with a set of strict=3D20
routing rules for some typical embedded 440GX
applications, then=3D20
someone should be able to design a board with
these rules and not have
=20
to run simulations. Reliability should be fine
if
they do their job=3D20
right, time to market will be short, and cost
will
be low.
-tom
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx=3D20=20
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ed Sayre III
Sent: Monday, November 08, 2004 9:33 AM
To: pm_norge@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR SDRAM signal routing
Peter,
You NEED to run simulations. I have worked
on
DDR SDRAMs=3D20
architectures=3D3D20 for many years now and
every
one was slightly=3D20
different. You can benefit=3D3D20 greatly from
simulations since it=3D20
generates your skew budget, component=3D3D20
placement and proper=3D20
termination among other design points. If
you=3D3D20 management tells =3D
you
=20
that they are willing to spend the money on
repeated=3D3D20 turns, where =3D
=20
you may or may not find the right answer, then
you
are wasting=3D3D20 =3D
your
=20
money. Either hire a consultant with experience
in the area of DDR
memory or develop your own in house
expertise.=20
There are many people=3D20
and=3D3D20
products available right now. The driving
force
behind all this is
time=3D3D20
to market and system reliability.
Good luck
-Ed Sayre
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
NORTH EAST SYSTEMS ASSOCIATES,
INC
=3D
-------------------------------------=3D3D20
"High Performance
Engineering & Design"
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Dr. Edward Sayre 3rd e-mail:
esayre3@xxxxxxxx
NESA, Inc. =20
http://www.nesa.com/
5 Lan Drive, Suite 200 Tel=20
+1.978.392-8787 x 218
Westford, MA 01886 USA Fax
+1.978.392-8686
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
At 09:32 AM 11/8/2004 +0000, you wrote:
I have been designing different kinds of
electronic products, but=3D20
never
a DDR SDRAM interface with 16 memory
chips
(MT46V64M8, 512Mb =3D
=20
=3D=3D=3D message truncated =3D=3D=3D
=09
__________________________________
Do you Yahoo!?=20
Check out the new Yahoo! Front Page.=20
www.yahoo.com=20
=20
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--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com
Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC
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Old (prior to June 6, 2001) list archives are viewable at:
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