FreeLists / si-list / [SI-LIST] Re: DDR SDRAM signal routing

[<art_porter@xxxxxxxxxxx>]

I heard an analogy a few years back that I thought was pretty good: =
Designing any kind of high-speed digital electronics without simulation =
is like driving at night wiht your lights off.

Art Porter

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ed Sayre III
Sent: Monday, November 08, 2004 10:33 AM
To: pm_norge@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR SDRAM signal routing


Peter,
   You NEED to run simulations.  I have worked on DDR SDRAMs =
architectures=20
for many years now and every one was slightly different.  You can =
benefit=20
greatly from simulations since it generates your skew budget, component=20
placement and proper termination among other design points.  If you=20
management tells you that they are willing to spend the money on =
repeated=20
turns, where you may or may not find the right answer, then you are =
wasting=20
your money.  Either hire a consultant with experience in the area of DDR =

memory or develop your own in house expertise.  There are many people =
and=20
products available right now.    The driving force behind all this is =
time=20
to market and system reliability.

Good luck
-Ed Sayre


  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               NORTH EAST SYSTEMS ASSOCIATES, INC
                             -------------------------------------=20

                         "High Performance Engineering & Design"
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  Dr. Edward Sayre 3rd            e-mail: esayre3@xxxxxxxx
  NESA, Inc.                              http://www.nesa.com/
  5 Lan Drive, Suite 200          Tel  +1.978.392-8787 x 218
  Westford, MA 01886 USA       Fax +1.978.392-8686
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



At 09:32 AM 11/8/2004 +0000, you wrote:
>I have been designing different kinds of electronic products, but never =
a
>DDR SDRAM interface with 16 memory chips (MT46V64M8, 512Mb chip, 8-bit =
@
>167MHz)and 2 ECC chips (same type).
>
>Between the processor (IBM PowerPC 440GX) and memory chips there are =
only
>the transmission lines and series termination resistors (25Ohm close to =
the
>processor). I do not have the possibility to run simulations, so it's
>learning by doing.
>
>The data lines are around 60-70mm and the address line around 250mm!!! =
long.
>I'm afraid I will get serious SI problems with this configuration. I =
read
>some Appnotes but I could really use some help from experienced SI
>designers. What kind of termination do I really have to implement and =
what
>do I have to look out for?
>
>Thanks in advance
>Peter
>
>_________________________________________________________________
>Last ned MSN Messenger gratis http://www.msn.no/computing/messenger - =
Den
>korteste veien mellom deg og dine venner
>
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