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Thread Index for si-list, 11-2003

[si-list] || [11-2003 Date Index] [11-2003 Thread Index]

  1. [SI-LIST] Re: Books/references on power/ground distribution, Lee Ritchey
  2. [SI-LIST] Spice simulators help, Preethi Kundoor
  3. [SI-LIST] Re: Books/references on power/grounddistribution, Youssef Khalife
  4. [SI-LIST] Inappropriate remarks and personal attacks, Mike Brown
  5. [SI-LIST] About common-mode, "Fu, Greg (付?操 IES)"
  6. [SI-LIST] Book Price, Chris Landrum x311
  7. [SI-LIST] FW: Re: Book Price, Rich Peyton
  8. [SI-LIST] Re: FW: Re: Book Price, Marowsky, Rich
  9. [SI-LIST] STOP MOANING, Ashar, Nimish (EU-SES)
  10. [SI-LIST] Re: About common-mode, Knighten, Jim L
  11. [SI-LIST] Regarding all the 'book price' traffic, Raymond Anderson
  12. [SI-LIST] breakdown voltage (arching) equation, gustavo . duenas
  13. [SI-LIST] Return Current of High-speed transmission line., ªü¥È
  14. (no subject), vince vintero
  15. [SI-LIST] Re: (no subject), Raymond Anderson
  16. [SI-LIST] inductance of a reflowed solder bump, Firas Azrai
  17. [SI-LIST] Re: breakdown voltage (arching) equation, Salkow, Steven
  18. [SI-LIST] All Digital Phase Locked Loop, vamshi krishna lakkaraju
  19. [SI-LIST] Power homework, was: RE: (no subject), Brown, Mike (Austin, TX)
  20. [SI-LIST] Meeting Announcement: IPC-SVC on Nov. 11 in San Jose, Bob McCreight
  21. [SI-LIST] Best Method to measure Characteristic Impedance on a PCB Board, Shiraz Bashir
  22. [SI-LIST] Re: EMC, Chin, Dominic Kin Hii
  23. [SI-LIST] Recall: EMC, Chin, Dominic Kin Hii
  24. [SI-LIST] impedance mismatch, Chin, Dominic Kin Hii
  25. [SI-LIST] Book from Bakoglu: Circuits, Interconnections, and Packaging for VLSI, manthos labropoulos
  26. [SI-LIST] EMC, Chris Landrum x311
  27. [SI-LIST] Re: impedance mismatch, Chris Landrum x311
  28. [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice., penlmml
  29. [SI-LIST] SI/CAD engineer available for employment, Praveen Soora
  30. [SI-LIST] Lee Ritchey's book, steve weir
  31. [SI-LIST] Recommendation for quick-turn board house, Stuart Brorson
  32. [SI-LIST] Antw: Embedded uStrip - double check me, Robert Nowak
  33. [SI-LIST] Question about implementing capacitors on IC, Guo Yawei
  34. [SI-LIST] Re: Question about implementing capacitors on IC, Goel Mayank (IFIN DC DAT)
  35. [SI-LIST] FW: Embedded uStrip - double check me, WALKER, Mark
  36. [SI-LIST] PECL to CMOS conversion, Chris Landrum x311
  37. [SI-LIST] Re: Antw: Embedded uStrip - double check me, Chris McGrath
  38. [SI-LIST] IBIS Models, Gibson, Guy (ES)
  39. [SI-LIST] Re: IBIS Models, keefe_bohannan
  40. [SI-LIST] unsubscribe, Alvin B. Rogers
  41. [SI-LIST] Re: Embedded uStrip - double check me, bdempsey85
  42. [SI-LIST] relative magnetic permeability of tungsten, molybdenum... proving hard to find, WALKER, Mark
  43. [SI-LIST] SI tools, Chris Landrum x311
  44. [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... provinghard to find, D G
  45. [SI-LIST] IBIS series component example files, gilbkr
  46. [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find, Knighten, Jim L
  47. [SI-LIST] Re: SI tools, Support Hyperlynx
  48. [SI-LIST] About the concept, "Fu, Greg (付?操 IES)"
  49. [SI-LIST] Re: relative magnetic permeability of tungsten, molybde num... proving hard to find, Bart Bouma
  50. [SI-LIST] Linear/Switching Power Supplies, Adeel Malik
  51. [SI-LIST] Re: Digest Number 896, Thomas Beneken
  52. [SI-LIST] Good morning, Jonathan Therrien
  53. [SI-LIST] Re: relative magnetic permeability of tungsten,mol ybdenum... proving hard to find, Aubrey_Sparkman
  54. [SI-LIST] Re: Lee Ritchey's book, Lee Ritchey
  55. [SI-LIST] si engineer wanted, bruce harvie
  56. [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find, D G
  57. [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find, Tabatchnick, Justin
  58. [SI-LIST] question about hspice, Zhangkun
  59. [SI-LIST] Resistor construction for high frequency operation, Mike Kauffman
  60. [SI-LIST] Question Regarding Simulations, Abdulrahman Rafiq
  61. [SI-LIST] req. for information ralted to Nx64 service, venu
  62. [SI-LIST] Re: question about hspice, Clewell, Craig
  63. [SI-LIST] Reminder: SCV EMC Society Mtg; Prof. Todd Hubing, Nov. 11 in Santa Clara, hansm
  64. [SI-LIST] inner Xtalk of a differential pair, Zhou, Xingling (Mick)
  65. [SI-LIST] Heisenberg in the Frequency Domain, Doug Smith
  66. [SI-LIST] SI Intro for your review (If you need support on High Speed Design and Signal Integrity), Jacque@xxxxxxxxxxxxxx
  67. [SI-LIST] the effect of power noise on IC, Zhangkun
  68. [SI-LIST] pci Ton and Toff test load, Ivor Ting
  69. [SI-LIST] RMCEMC December Social Event and Technical Presentation, Charles Grasso
  70. [SI-LIST] Curve Tracing IO pins at high state, Gian YK-r58635
  71. [SI-LIST] SPICE model of 74VHC04 and SN74LV123A, Zhangkun
  72. [SI-LIST] How do you unsubscribe to this list?, Jacobson, Richard
  73. [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity), Loyer, Jeff
  74. [SI-LIST] Re: inner Xtalk of a differential pair, Loyer, Jeff
  75. [SI-LIST] Re: SI Intro for your review (If you need support o n High Speed Design and Signal Integrity), Sgammato Chuck-ECS016
  76. [SI-LIST] Re: Resistance of Earth, EMCCOMPLY
  77. [SI-LIST] Job Opening- Lead SI engineer, SunMan Engineering, Inc.
  78. [SI-LIST] Re: How do you unsubscribe to this list?, Clewell, Craig
  79. [SI-LIST] Re: Regarding all the 'book price' traffic, Lee Ritchey
  80. [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity), Muranyi, Arpad
  81. [SI-LIST] Re: SI Intro...., Bob McCreight
  82. [SI-LIST] Where can I get DDR2 EBD or design file?, Jack W.C. Lin
  83. [SI-LIST] Re: Where can I get DDR2 EBD or design file?, slai
  84. [SI-LIST] =?big5?q?=A6^=ABH=A1G?= Where can I get DDR2 EBD ordesign file?, Sogo Hsu
  85. [SI-LIST] TDR Recommendations, Ray Haynes
  86. [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity), Craig . Sullivan
  87. [SI-LIST] SDRAM Timing, Ched-Chang Chai
  88. [SI-LIST] Re: [OT] Offshore engineering, Zabinski, Patrick J.
  89. [SI-LIST] FW: Samtec Connector Wizard Webinar - Connector Models, Corey Kimble
  90. [SI-LIST] Re: TDR Recommendations, Loyer, Jeff
  91. [SI-LIST] Re: PLEASE QUIT THIS STUFF and GET TECHNICAL AGAIN!, Robert Kezer
  92. [SI-LIST] Capacitor Vendor, Haddadin, Farah
  93. [SI-LIST] Right The First Time (the book), Mark Alexander
  94. [SI-LIST] Scattering parameters for "typical" vias, Stefan Ludwig
  95. [SI-LIST] Hspice Network Analysis, Bill . Cohen
  96. [SI-LIST] SSTL2 / HSTL Input buffer, Srinivasan JJ (ASIC) - CTD, Chennai.
  97. [SI-LIST] Re: SSTL2 / HSTL Input buffer, Robert Kezer
  98. [SI-LIST] Transmission line match, Doug Brooks
  99. [SI-LIST] Re: Transmission line match, Ross_Amans
  100. [SI-LIST] Proposed Launch (was TDR Recommendations), Ray Haynes
  101. [SI-LIST] HSPICE Problem: **warning** element name <oldname> is truncated as <newname>, Calin Brabandt
  102. [SI-LIST] For check, Harjeet Singhrandhwa
  103. [SI-LIST] Antw: Scattering parameters for "typical" vias, Robert Nowak
  104. [SI-LIST] QDRII clock design, Jean_Pierre . Bouthemy
  105. [SI-LIST] Hypertransport(HT) to Ethernet Bridge solutions, Harjeet Singhrandhwa
  106. [SI-LIST] Re: QDRII clock design, Robert Kezer
  107. [SI-LIST] Re: HSPICE Problem: **warning** element name <oldname> is truncated as <newname>, Clewell, Craig
  108. [SI-LIST] Regarding postings to si-list, Rich Peyton
  109. [SI-LIST] Re: Hspice Network Analysis, Bill . Cohen
  110. [SI-LIST] IMD and substrate thickness, Amitava Bhaduri
  111. [SI-LIST] Hspice subckt call, ElecQs quest
  112. [SI-LIST] Hspice Network Analysis now correlates, Bill . Cohen
  113. [SI-LIST] HSPICE Problem: **warning** Inconsistent data between The computed Vmaxand the given value : Rising Waveform, Feng F. Zhang
  114. [SI-LIST] How to solve HSPICE Warning: underflow, LIN ZHANG
  115. [SI-LIST] =?big5?q?=A6^=ABH=A1G?= RE: HSPICE Problem: **warning** Inconsistent data between The computedVmax and the given value : Rising Waveform, Feng F. Zhang
  116. [SI-LIST] Re: HSPICE Problem: **warning** Inconsistent data between Thecomputed Vmax and the given value : Rising Waveform, Feng F. Zhang
  117. [SI-LIST] stupid VNA / TDR / TDT Measurement / Setup question, hermann . ruckerbauer
  118. [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office., tmtokar
  119. [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question, Thomas Beneken
  120. [SI-LIST] Re: HSPICE Problem: **warning** Inconsistent data between The computed Vmax and the given value : Rising Waveform, Muranyi, Arpad
  121. [SI-LIST] Kelvin Functions, Dr. Edward P. Sayre
  122. [SI-LIST] PSPICE AC Sweep, Michael Smith
  123. [SI-LIST] Doug Brooks's Question, Sainath Nimmagadda
  124. [SI-LIST] EM simulation, Huiyun Li
  125. [SI-LIST] Re: EM simulation, Guo Yawei
  126. [SI-LIST] Cmos I/O & GTL I/O, Parthasarathy Sampath
  127. [SI-LIST] Fwd: RE: Doug Brooks's Question, Sainath Nimmagadda
  128. [SI-LIST] Fwd: RE: Re: Doug Brooks's Question, Sainath Nimmagadda
  129. [SI-LIST] Re: Cmos I/O & GTL I/O, Sunil Chandra KASANYAL
  130. [SI-LIST] IBIS Model error, Suresh.K
  131. [SI-LIST] Re: PSPICE AC Sweep, Thomas Beneken
  132. [SI-LIST] Re: IBIS Model error, Chris McGrath
  133. [SI-LIST] Re: Doug Brooks's Question, Sainath Nimmagadda
  134. [SI-LIST] Question, Rich Peyton
  135. [SI-LIST] Dear Doug Brooks, Sainath Nimmagadda
  136. [SI-LIST] Thomas Krzesaj/genius is out of the office., tkrzesaj
  137. [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity), Kai, Francis
  138. [SI-LIST] WG: stupid VNA / TDR / TDT Measurement / Setup question, hermann . ruckerbauer
  139. [SI-LIST] Dead Band in PLL, Parthasarathy Sampath
  140. [SI-LIST] Re: WG: stupid VNA / TDR / TDT Measurement / Setup question, Loyer, Jeff
  141. [SI-LIST] Signal Integrity / Package Modeling Job Opening, Steven Rosser
  142. [SI-LIST] Re: Dead Band in PLL, Chris Cheng
  143. [SI-LIST] Compensation scheme in two-stage opamp, Guo Yawei
  144. [SI-LIST] Re: Compensation scheme in two-stage opamp, Raymond . Leung
  145. [SI-LIST] what is the highest IBIS model being supported by hyperlynx, karan bagga
  146. [SI-LIST] what is the major difference b/w Ibis 3.2 & 3.3, karan bagga
  147. [SI-LIST] Re: Curve Tracing IO pins at high state, Gian YK-r58635
  148. [SI-LIST] Re: what is the highest IBIS model being supported by hyperlynx, Chris McGrath
  149. [SI-LIST] Re: what is the major difference b/w Ibis 3.2 & 3.3, Mirmak, Michael
  150. [SI-LIST] Noise in PCB vias, Jean_Pierre . Bouthemy
  151. [SI-LIST] s2ibis2 utility, hshankar61
  152. [SI-LIST] Algorithm to interpolate ramp data in IBIS, BHAGWATH,NITIN (HP-Roseville,ex1)
  153. [SI-LIST] FW: [HireTopTalent-Ottawa] Job Opportunity, Paul Dobrovolny
  154. [SI-LIST] charge Pump Current in PFD, Parthasarathy Sampath
  155. [SI-LIST] Re: charge Pump Current in PFD, Guo Yawei
  156. [SI-LIST] Re: s2ibis2 utility, Chris McGrath
  157. [SI-LIST] EMI/EMC Conference in Chennai, India, Sambandam Karunakaran
  158. [SI-LIST] IBIS models - not all created equal?, Grasso, Charles
  159. [SI-LIST] Re: IBIS models - not all created equal?, Morgenstierne, Christian
  160. [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS, BHAGWATH,NITIN (HP-Roseville,ex1)
  161. [SI-LIST] Re: TDR and line losses, Loyer, Jeff
  162. [SI-LIST] Fastcap main manual, Rakeshmrak
  163. [SI-LIST] Re: PCB Design Guidelines, rsefton@xxxxxxxxxxxxx
  164. [SI-LIST] IBIS ICM 1.0.0 Parser On-line!, Mirmak, Michael
  165. [SI-LIST] Reflection problem due to multi drop of shard bus, #CHUANG KENG HUA#
  166. [SI-LIST] Current Sharing of Parallel -48V Power supplies, D.Rajasekar
  167. [SI-LIST] high speed PCB design, sunil Morajkar
  168. [SI-LIST] various system backplanes, venu
  169. [SI-LIST] R: high speed PCB design, Guasti Giovanni
  170. [SI-LIST] ESD and connector testing, Nadolny, Jim
  171. [SI-LIST] RMCEMC Dec meeting - Registration closes Dec 1st, Grasso, Charles
  172. [SI-LIST] HSPICE stimulus question, David Kaiser
  173. [SI-LIST] Re: HSPICE stimulus question, Robert Kezer
  174. [SI-LIST] Dielectric constant for FR4 at above 1Ghz frequency, Andy Kuo
  175. [SI-LIST] Hspice T-elements in AC sweep?, Fasig, Jonathan L.
  176. [SI-LIST] Hspice Fieldsolver Question, Liu, Bowen
  177. [SI-LIST] s2ibis2 Spice model file specification, hshankar61
  178. [SI-LIST] Split Vdd for DDR, Abhijit Mahajan
  179. [SI-LIST] Separating SSO contributed by board vs device, Fabrizio Zanella
  180. [SI-LIST] "dominant" losses, Loyer, Jeff
  181. [SI-LIST] Re: "dominant" losses, Dimiter Popoff
  182. [SI-LIST] Re: Hspice Fieldsolver Question, Liu, Bowen
  183. [SI-LIST] second call for papers: ICCS 2004:Workshop on Simulation and Modeling of 3D Integrated Circuits, Igor Balk
  184. [SI-LIST] Transmission Lines Information, Venkata Ramana
  185. [SI-LIST] MDIO HW/SW, Paul Park
  186. [SI-LIST] TDR and line losses, Eric Bogatin
  187. [SI-LIST] 6 layers PCB, Moustapha Abdi Hassan
  188. [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency, Fasig, Jonathan L.
  189. [SI-LIST] Signal Conditioning Cable Assemblies, Moeller, Merrick
  190. [SI-LIST] clock divider, Ahmet Tokuz
  191. [SI-LIST] Two PLL's sequentional connection, David Shapiro
  192. [SI-LIST] Via model, Dorin
  193. [SI-LIST] R: Re: clock divider, Guasti Giovanni
  194. [SI-LIST] Internal inductance model, Geoff Stokes
  195. [SI-LIST] six layers board, Moustapha Abdi Hassan
  196. [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question, Geoff Stokes
  197. [SI-LIST] Parallel plate mode, Geoff Stokes
  198. [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency, Papa November
  199. [SI-LIST] VHDL-AMS, Mohanty, Girish C. (UMR-Student)
  200. [SI-LIST] Re: VHDL-AMS, Donnelly, Mike
  201. [SI-LIST] Looking for SPICE Model, Zhangkun



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