FreeLists / si-list / [SI-LIST] Re: EMC

[vasudevan.duraiswamy@xxxxxxxxxxx]

Hi,

    I agree with Chris,  about SI with adjacent  Power or GND  layers.

my comments & suggessions

 no need for GND filling in the external layers.
provide reasonale edge clearance for routing in external layers & inner layers
better to use inner layers as planes instead of filling
 you can consider changing the layer stack in a way to get better power 
intergrity & SI

With Best Regards,

Vasudevan D
Sr.Technical Leader - PCB Design
Philips Digital Systems Lab
Philips Innovation Campus, #1, Murphy Road, Bangalore - 560 008
Telephone: +91-80-557-9000 x5030
Fax : +91-80-554-6645


                                                                                
                                                                       
                                                                                
                                                                       
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                                                   Subject:    [SI-LIST] EMC    
                                                                       
                                                                                
                                                                       
               "subramani"                         Classification:              
                                                                       
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Hello,

I am doing a board design. It has to pass stringent EMI tests.

Mine is a 10 layer board.

The board stack up is
1    TOP component, GND filling
2    Power
3    signal
4    GND filling
5    signal
6    Signal
7    GND filling
8    Signal
9    Power
10  Bottom Component, GND filling

The board has SDRAM operating at 100Mhz. Where should I route the clocks.
Could anyone tell me about the ways and means of reducing EMI.
The SDRAM is placed that is near to the edge of PCB. Will it cause
radiation.
Is there a formula for keepout distance.

Regards
Subramani
Mistral


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