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Thread Index for si-list, 11-2002

[si-list] || [11-2002 Date Index] [11-2002 Thread Index]

  1. [SI-LIST] Re: FET Probe, Jim Roberts
  2. [SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter?, Mike Brown
  3. [SI-LIST] Physical layer design/test position, Nitin Bhandari
  4. [SI-LIST] AC Analysis in Hspice, Loyer, Jeff
  5. [SI-LIST] What it takes to be a Signal Integrity Expert, Shiraz Bashir
  6. [SI-LIST] Presentation available for download & November Meeting, Charles Grasso
  7. [SI-LIST] Presentation available for download & November Meeting - Take2, Charles Grasso
  8. [SI-LIST] Measuring volgage across seams, Doug Smith
  9. [SI-LIST] Re: AC Analysis in Hspice, Ye, Xiaoning
  10. [SI-LIST] doing measurements in Hspice, Yoni Tzafrir
  11. [SI-LIST] Audio Amplifier, Adeel Malik
  12. [SI-LIST] DC resistance calculation of returen path_equivalent width?, Sogo Hsu
  13. [SI-LIST] Via-In-Pad or Via-Next-To-Pad - which is best?, JP Nicholls
  14. [SI-LIST] Re: Via-In-Pad or Via-Next-To-Pad - which is best?, Ray Anderson
  15. [SI-LIST] Re: Capacitance Formula, Gupta, Deepali
  16. [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option, Daniel, Erik S., Ph.D.
  17. [SI-LIST] about ABT tech and a basic question, qzheng
  18. [SI-LIST] SI Contractor Position Opening, Ma, Samuel E
  19. [SI-LIST] MEASUREMENT OF POWER-DISTRIBUTION NETWORKS AND ITS ELEMENTS, istvan novak
  20. [SI-LIST] Re: DC resistance calculation of returen path_equivalent width?, John Lin (???)
  21. [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option, D G
  22. [SI-LIST] John Cooley article in EE Times, Joe Socha
  23. [SI-LIST] Re: EMI/EMC software, k EPD
  24. [SI-LIST] Smartspice vs Hspice?, Zabinski, Patrick J.
  25. [SI-LIST] About IBIS error from IBIS check, Jack W.C. Lin
  26. [SI-LIST] backplane docs link, qzheng
  27. [SI-LIST] IBIS model for CML differential buffers, Mohammad Ali
  28. [SI-LIST] Re: About IBIS error from IBIS check, Ingraham, Andrew
  29. [SI-LIST] Hspice problems with [Driver_Schedule] IBIS buffers, Linnenbruegger Dirk
  30. [SI-LIST] Re: IBIS model for CML differential buffers, Timothy Coyle
  31. [SI-LIST] Re: HSPICE & Common Model Interface, Ray Anderson
  32. [SI-LIST] Off topic - IC package marking, Rotem Gazit
  33. [SI-LIST] Re: Off topic - IC package marking, Michael_Greim
  34. [SI-LIST] Hysteresis in LVDS receiver., rajesh . kaushik
  35. [SI-LIST] Basic IBIS I/V curve question, marko.pulli
  36. [SI-LIST] Re: Basic IBIS I/V curve question, Ingraham, Andrew
  37. [SI-LIST] Voltage Drop, AK Mishra
  38. [SI-LIST] Re: Voltage Drop, Zabinski, Patrick J.
  39. [SI-LIST] Equalization of transmission lines?, Doug Brooks
  40. [SI-LIST] Re: Equalization of transmission lines?, Keskinen, Kai
  41. [SI-LIST] Off Topic Question, Bill Reams
  42. [SI-LIST] Re: Off Topic Question, Jackson, T L
  43. [SI-LIST] PCI : 5V clock to non-5V tolerant clock input, Adam Barnes
  44. [SI-LIST] Re: which one is better, Javier del Valle
  45. [SI-LIST] Re: PCI : 5V clock to non-5V tolerant clock input, Ingraham, Andrew
  46. [SI-LIST] FW: Off Topic Question, Bill Reams
  47. [SI-LIST] si Engineer, Ed Beckett
  48. [SI-LIST] Decaps. in a BGA package..??, Virendra
  49. [SI-LIST] Re: Decaps. in a BGA package..??, Volk, Andrew M
  50. [SI-LIST] Signal Integrity Position in our team, Roger Roger
  51. [SI-LIST] Recruiter Postings, Ray Anderson
  52. [SI-LIST] floating metals, Zhou, Xingling (Mick)
  53. [SI-LIST] About Software and IBIS question, Thomas Krzesaj
  54. [SI-LIST] signal to noise ratio of a connector, Lin Wee
  55. [SI-LIST] Softwares & IBIS questions..., Thomas Krzesaj
  56. [SI-LIST] Re: IBIS Model monotonocity and ICX and ibischk, Abhijit Mahajan
  57. [SI-LIST] Re: signal to noise ratio of a connector, Clewell, Craig
  58. [SI-LIST] Re: IBIS Model monotonicity and ICX and ibischk, Beal, Weston
  59. [SI-LIST] Power/Ground Net modeling in TPA ..., Neeraj Pendse
  60. [SI-LIST] Clock net correlation_current mode current steeling, Sogo Hsu
  61. [SI-LIST] Registered DDR 266/333 model?, Sogo Hsu
  62. [SI-LIST] Signal Interface within CML and LVDS?, Inmyung Song
  63. [SI-LIST] Re: Power/Ground Net modeling in TPA ..., Anil Pannikkat
  64. [SI-LIST] Decoupling of Oscillator, Zhangkun
  65. [SI-LIST] octal Gigabit Ethernet PHY, Raja
  66. [SI-LIST] Re: Registered DDR 266/333 model?, Michael_Greim
  67. [SI-LIST] Books for Mixed-Mode S matrix, Shiming Wang
  68. [SI-LIST] Effect of contact resistance on high frequency signals, Keskinen, Kai
  69. [SI-LIST] Re: Books for Mixed-Mode S matrix, D G
  70. [SI-LIST] Re: Decoupling of Oscillator, EVANS,JEFF (HP-Cupertino,ex3)
  71. [SI-LIST] Surface mount vs. through hole at 1.5 to 3 Gbps, Mike Haff
  72. [SI-LIST] Re: Surface mount vs. through hole at 1.5 to 3 Gbps, Gupta, Deepali
  73. [SI-LIST] The stimulus rise/fall time in hspice, zanglinyuan
  74. [SI-LIST] Re: Effect of contact resistance on high frequency signals, boris . traa
  75. [SI-LIST] running rlgc file, Yoni Tzafrir
  76. [SI-LIST] Re: running rlgc file, ruston, matt
  77. [SI-LIST] Close field measurement method, Thomas Krzesaj
  78. [SI-LIST] Re: The stimulus rise/fall time in hspice, Patrick_Carrier
  79. [SI-LIST] EDN Access 09.01.95 Don't let rules of thumb set decoupling-capacitor values, Grasso, Charles
  80. [SI-LIST] Re: Traces under converters - bad mojo or myth?, Ivor Bowden
  81. [SI-LIST] Flight Time, Bob Patel
  82. [SI-LIST] Re: Flight Time, Grigoras, Adrian C
  83. [SI-LIST] ASIC core level and package level SI issues., Abhijit Dutta
  84. [SI-LIST] PCI I/O design, rajat . chauhan
  85. [SI-LIST] Dynamic Clamp, Timothy Coyle
  86. [SI-LIST] Re: Surface mount SMB, Loyer, Jeff
  87. [SI-LIST] Sample Projects or Designs for Mentor Graphics ICX Tool, Embedded Online
  88. [SI-LIST] signal source distribution and jitter question, C Deibele
  89. [SI-LIST] How to make SPICE model of bead, Zhangkun
  90. [SI-LIST] A question about XTK, Jack W.C. Lin
  91. [SI-LIST] flight time = propagation delay?, =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
  92. [SI-LIST] Effect of Stub-Length on Max. Length Calculation, Adeel Malik
  93. [SI-LIST] QQuestion: DC Ohm's law , rot E is zero ? at wire surface, ikanno
  94. [SI-LIST] Re: flight time = propagation delay?, Clewell, Craig
  95. [SI-LIST] Re: Effect of Stub-Length on Max. Length Calculation, chris . mcgrath
  96. [SI-LIST] Re: signal source distribution and jitter question, C Deibele
  97. [SI-LIST] Re: A question about XTK, Abe Riazi
  98. [SI-LIST] ECL or LVDS?, Juan Manuel
  99. [SI-LIST] GMII over Board-to-Board Connector, Paul Strachan
  100. [SI-LIST] Re: ECL or LVDS?, Bill . Cohen
  101. [SI-LIST] bring files from Pspice 8 to Pspice 9.1, Angus Yang
  102. [SI-LIST] differential signaling terminator., Juan Manuel
  103. [SI-LIST] Pictures of TC77b meeting in Arizona, Doug Smith
  104. [SI-LIST] running rlgc file - conclusion...and special thanks to you matt, Yoni Tzafrir
  105. [SI-LIST] T1/E1 Tutorial published !, Eitan k
  106. [SI-LIST] T1/E1 Tutorial published !, Eitan k
  107. [SI-LIST] pc2700 simulation models, Schaefer, Andreas (Abg)
  108. [SI-LIST] Re: Softwares & IBIS questions..., stephanie . goedecke
  109. [SI-LIST] Allegro Question, Kipnis, Oleg
  110. [SI-LIST] RMCEMC November Meeting Reminder & Restaurant update, Charles Grasso
  111. [SI-LIST] Re: Allegro Question, Mike Barham
  112. [SI-LIST] SABER parts to PSpice parts, Alicia Corrales Chanca
  113. [SI-LIST] Advise on PCB dessign software, joan vicent castell
  114. [SI-LIST] Layout to allegro, Kevin Buchanan
  115. [SI-LIST] Sorry incorrect forum...., Kevin Buchanan
  116. [SI-LIST] Signal Integrity Classes: December, Gary Otonari
  117. [SI-LIST] COnsecutive 0's or 1's in 4b5b encoded data, Bob Patel
  118. [SI-LIST] QQuestion: Radiation, in inquiry time of Terminator value ?, ikanno
  119. [SI-LIST] question about using headers in power distribution ?, Anand Kulkarni
  120. [SI-LIST] Diode in test load, Virendra
  121. [SI-LIST] Re: Diode in test load, Virendra
  122. [SI-LIST] Re: A question about ansoft, Nirmal Sharma
  123. [SI-LIST] Re: question about using headers in power distribution ?, Ruturaj Pathak
  124. [SI-LIST] Theoretical Battery Life, Mike Neaves
  125. [SI-LIST] Re: Theoretical Battery Life, Feldman, Richard
  126. [SI-LIST] PCI-X in Specctraquest, Lucas Bossetti
  127. [SI-LIST] Re: PCI-spec question, Ingraham, Andrew
  128. [SI-LIST] Home-brewed Power-Over-Ethernet? OT?, Steven Kan
  129. [SI-LIST] Re: Home-brewed Power-Over-Ethernet? OT?, Gupta, Anurag x4500
  130. [SI-LIST] Creaging Pseudo Random Bit Sequence (PRBS) stimuli for Hspice, Fasig, Jonathan L.
  131. [SI-LIST] Re: Creaging Pseudo Random Bit Sequence (PRBS) stimuli for Hspice, Ray Anderson
  132. [SI-LIST] more on PWL statement generation for PRBS simulation in spice, Ray Anderson
  133. [SI-LIST] for design and high speed engg, Nimish Aggarwal
  134. [SI-LIST] PCB layout: How to choose allowable crosstalk?, Kolstad, Joel (EIP)
  135. [SI-LIST] [IBIS-Users] IBIS Questions, Shee Kian Wong
  136. [SI-LIST] Cascading differential 2-Port Networks, Bob Welte
  137. [SI-LIST] Re: more on PWL statement generation for PRBS simulation in spice, Keskinen, Kai
  138. [SI-LIST] AW: Re: more on PWL statement generation for PRBS simulatio n in spice, hermann . ruckerbauer
  139. [SI-LIST] Re: more on PWL statement generation for PRBS simul atio n in spice, Keskinen, Kai
  140. [SI-LIST] Re: Creating Pseudo Random Bit Sequence (PRBS) stimuli for Hspic, Steven Kan
  141. [SI-LIST] FW: Impedance / stackup calculations and ApsimRLGC, Kevin Buchanan
  142. [SI-LIST] Re: Cascading differential 2-Port Networks, D G
  143. [SI-LIST] HSTL technology, Fabrizio Zanella
  144. [SI-LIST] All you want for Xmas is to sim at Dell, Dude...., Michael_Greim
  145. [SI-LIST] Re: Creating Pseudo Random Bit Sequence (PRBS) stimuli for Hspice, Ray Anderson
  146. [SI-LIST] mailed you an e-card -- Si-List., =?big5?b?U3RhbmxleS5DaGl1KKr0q6uyTSk=?=
  147. [SI-LIST] SORRRY, VIRUS., Juan Manuel
  148. [SI-LIST] MICROVIA CAPACITANCE, Juan Manuel
  149. [SI-LIST] Seeking sources for hard-2-find tech books, Grasso, Charles
  150. [SI-LIST] FW: Seeking sources for hard-2-find tech books use www.addall.com, Steinkogler, Gary
  151. [SI-LIST] Re: Seeking sources for hard-2-find tech books, Ray Anderson
  152. [SI-LIST] position available, Ron Miller
  153. [SI-LIST] Re: Multiple Job Opportunities, Pat Diao
  154. [SI-LIST] Error in HSPICE, Bob Patel
  155. [SI-LIST] AW: How to make SPICE model of bead, Linnenbruegger Dirk
  156. [SI-LIST] harmonics, Atul Rastogi
  157. [SI-LIST] transformer, Atul Rastogi
  158. [SI-LIST] problem, Atul Rastogi
  159. [SI-LIST] Re: Error in HSPICE, Clewell, Craig
  160. [SI-LIST] compact PCI clock frequency, Nico Fleurinck
  161. [SI-LIST] Re: compact PCI clock frequency, Ingraham, Andrew
  162. [SI-LIST] Re: transformer, Clewell, Craig
  163. [SI-LIST] Re: mailed you an e-card -- Si-List. WARNING about Virus in previous message with this subject., jeff_latourrette
  164. [SI-LIST] Please suggest a way to monitor high speed busses, Gupta, Anurag x4500
  165. [SI-LIST] Re: Please suggest a way to monitor high speed busses, Gupta, Anurag x4500
  166. [SI-LIST] Yet another HSPICE error message, Gil Gafni
  167. [SI-LIST] Fwd: RE: harmonics, Atul Rastogi
  168. [SI-LIST] dear sir,=20, Atul Rastogi
  169. [SI-LIST] compact-PCI clock generation, Nico Fleurinck
  170. [SI-LIST] How to select the pullup/pulldwon resistor, peter zhu
  171. [SI-LIST] Star-Hspice working directory, Shee Kian Wong
  172. [SI-LIST] Re: How to select the pullup/pulldwon resistor, Michael Nudelman
  173. [SI-LIST] Via/Contact Resisance?, Pallav Gupta
  174. [SI-LIST] Power supply noise, Martin Euredjian




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