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[SI-LIST] Re: Impedance mismatch due to Cu pours
- From: "S.L.NARASIMHA MURTHY" <slnmurthy@xxxxxxxxxxx>
- To: Michael.Nagel@xxxxxxxx, Shankar.Raj@xxxxxxxxxx
- Date: Sun, 11 Nov 2001 15:22:38 +0530
Hi Shankar
As regards the usage of split planes, one reservation I have is placing them
next to the top and bottom layers. As the propagation velocity of the
signalsis the highest on the two outer layers , I would prefer to keep the
high speed signals on these layers and split planes next to them will create
higher inductance in the return current path irrespective of the slot width
and hence more EMC issues. I would prefer to avoid split planes in high
performance design. I would go in for the layer stack suggested by Alen:
1. Top (signal 1)
2. GND 1
3. Signal 2
4. Split Power 1
5. GND 2
6. Signal 3
7. GND 3
8. Bottom (signal 4)
S.L.N.Murthy ECAD Technologies Ltd.
Bangalore -11, PH: 656 2274/6565587
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