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[SI-LIST] Re: DDR2 CMD/CTRL vs. CK Skew compensation problems

  • From: Jory McKinley <jory_mckinley@xxxxxxxxx>
  • To: fanglv1@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Mon, 22 Oct 2007 08:09:37 -0700 (PDT)
A couple of points:
(1) Check the F slot design the almost 4000mils difference between CLK and CMD 
seems excessive.
(2) Typically routing lengths are minimized and tunning is done with the DLL.
(3) Typical CLK and CMD routing differences for this system are in the 
1000-3000mil range depending on driver type/board characteristics/DLL settings.

----- Original Message ----
From: LV Fang <fanglv1@xxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Cc: fanglv1@xxxxxxxxxxx
Sent: Monday, October 22, 2007 8:06:37 AM
Subject: [SI-LIST] DDR2 CMD/CTRL vs. CK Skew compensation problems 


Hi all,
I am trying to design one DDR2 EVB board with one DIMM slot working at 
667Mbps. During the board routing, I am planing to keep CMD/CTRL lengh 
matching with clk signal as possible as I can. However, when I did 
pre-layout SI simulation for CMD/CTRL vs. CLK(assuming unbufferd DIMM
 Card 
F has been inserted into the slot), the timing analysis results show
 that 
the CMD signal at receiver pad side has much longer flight time than
 clk 
signal, and sometimes CMD  is even sampled at the next clk cycle
 instead of 
the corresponding clk cycle, which violates the read latency and write 
latency requirements. I checked the topology and found that in
 unbufferd 
DIMM card F, CMD trace lengh is almost 100mm longer than the CK trace. 
Based on my understandings, two ways may solve this problem. One is
 tuning 
silicon IO DLL timing,the other is extending the clk lengh on the EVB 
board. My question is:
1. How can I balance the two methods? Is there the third way to slove
 this 
problem?
2. In your unbufferd DIMM card mother board design, typically how much 
length difference between CMD and CLK signal group?
3. if the Register DIMM card instead unbuffered DIMM card insert into
 slot, 
what's the length match requirement in mother board design? Shall I
 need 
set my read and write latency one more cycle or EPROM in DIMM card has
 done 
it automatically?

Really appreciate your inputs.

fang

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