Date Index for si-list, 10-2007

[si-list] || [10-2007 Date Index] [10-2007 Thread Index]

[SI-LIST] Re: AC Coupled Signals - istvan novak
[SI-LIST] Re: AC Coupled Signals - Loyer, Jeff
[SI-LIST] Re: si-list Digest V7 #326 - Dmitriev-Zdorov, Vladimir
[SI-LIST] Re: What to do with "isolation" conductors in ribbon cable? - Xin Wu
[SI-LIST] Free Webinar about Co-Design b/w IC and Package for Power Integrity - Patrick Lam
[SI-LIST] Re: AC Coupled Signals - istvan novak
[SI-LIST] Re: What to do with "isolation" conductors in ribbon cable? - stebla01
[SI-LIST] How to qualify Component Video(YPrPb)?? - Alex Li
[SI-LIST] Emission level vary for same type of SATA cables but different vendors - Kunal Sabavat
[SI-LIST] Re: How to qualify Component Video(YPrPb)?? - Jerry Chow
[SI-LIST] Re: How to qualify Component Video(YPrPb)?? - Jerry Chow
[SI-LIST] Emission level vary for same type of SATA cables but different vendors - Kunal Sabavat
[SI-LIST] Re: Emission level vary for same type of SATA cables but different vendors - McCoy, Bart
[SI-LIST] Re: Emission level vary for same type of SATA cables but different vendors - Eric Bogatin
[SI-LIST] Re: Emission level vary for same type of SATA cables but different vendors - Joel Brown
[SI-LIST] Re: Emission level vary for same type of SATA cables bu t different vendors - Clewell, Craig
[SI-LIST] Re: AC Coupled Signals - Loyer, Jeff
[SI-LIST] Re: AC Coupled Signals - Istvan Novak - Board Design Technology
[SI-LIST] Re: AC Coupled Signals - Stephen Zinck
[SI-LIST] DDR memory - Mohammad Haeri Kermani
[SI-LIST] Re: What to do with "isolation" conductors in ribbon cable? - Loyer, Jeff
[SI-LIST] noise injection for troubleshooting - Doug Smith
[SI-LIST] Re: AC Coupled Signals - Jeon, Tae-Kwang
[SI-LIST] First Pass System Success Workshop - Chris Herrick
[SI-LIST] Re: AC Coupled Signals - DrFWS
[SI-LIST] Re: AC Coupled Signals - Jeon, Tae-Kwang
[SI-LIST] Package Layout Resource - John Ellis
[SI-LIST] PCI, FPGA, Orcad BSEE Engineer needed at Mobilygen; - Mark Apton
[SI-LIST] Free Waveform viewer - Alam Poazee
[SI-LIST] prescalar - boli sudha
[SI-LIST] Re: prescalar - steve weir
[SI-LIST] Re: Free Waveform viewer - Alexandre . AMEDEO
[SI-LIST] Re: Free Waveform viewer - art_porter
[SI-LIST] Re: Free Waveform viewer - Stuart Brorson
[SI-LIST] DRAM capacitance - Vadim Heyfitch
[SI-LIST] Re: Free Waveform viewer - Tom Zych
[SI-LIST] Re: Request for example transmission line models and their 2d solver - Kirby Goulet
[SI-LIST] Re: Free Waveform viewer - Aubrey_Sparkman
[SI-LIST] IBIS HELP - Santos Fernandez, Jesus
[SI-LIST] Re: IBIS HELP - Kai Keskinen
[SI-LIST] Reminder: CIE-SF 2007 Annual Short Course, EPMC-04, Latest Development in High Performance Lead-Frame Packaging and Applications, this coming Saturday afternoon at SJSU Engineering Building Room 339 - Jin Zhao
[SI-LIST] Trace Width and Skin Effect Loss - J.Jebakumar Samuel
[SI-LIST] Re: Trace Width and Skin Effect Loss - steve weir
[SI-LIST] Re: Free Waveform viewer - Tom Zych
[SI-LIST] A ibis problem in Hyperlynx simulation - Han Li
[SI-LIST] Re: Trace Width and Skin Effect Loss - Peterson, James F (EHCOE)
[SI-LIST] Re: Free Waveform viewer - Tom Zych
[SI-LIST] Re: A ibis problem in Hyperlynx simulation - Powell, Jon N
[SI-LIST] Survey of SI analysis software - Meunier, Eric
[SI-LIST] Re: Trace Width and Skin Effect Loss - Yuriy Shlepnev
[SI-LIST] Re: Survey of SI analysis software - Kai Keskinen
[SI-LIST] Re: Survey of SI analysis software - Hargin, Bill
[SI-LIST] Re: Survey of SI analysis software - Hargin, Bill
[SI-LIST] Re: Survey of SI analysis software - Filip, Cristian
[SI-LIST] Re: Survey of SI analysis software - Hargin, Bill
[SI-LIST] R: Re: Trace Width and Skin Effect Loss - gianguida
[SI-LIST] Re: A ibis problem in Hyperlynx simulation - Kihong Joshua Kim
[SI-LIST] Re: Balun measurement - ronald miller
[SI-LIST] Re: Balun measurement - steve weir
[SI-LIST] SI Conferences and Workshops - Buchs, Kevin
[SI-LIST] Re: Balun measurement - ronald miller
[SI-LIST] Re: Balun measurement - steve weir
[SI-LIST] Sr. Signal Integrity Engineer Position Available @ Sun Microsystems, Inc. - Derek Tsai
[SI-LIST] Re: SI Conferences and Workshops - Fabrizio . Zanella
[SI-LIST] ADS Models from TDR/TDT data - ronald miller
[SI-LIST] Re: SI Conferences and Workshops - LEE E P
[SI-LIST] Gigabit ethernet compliance asymmetry test - ruston_matt
[SI-LIST] Re: Gigabit ethernet compliance asymmetry test - Kihong Joshua Kim
[SI-LIST] Help Explaining Microstrip - Paul Levin
[SI-LIST] Re: Help Explaining Microstrip - steve weir
[SI-LIST] Re: Help Explaining Microstrip - Mark Randol
[SI-LIST] Desperately Seeking SI - Tech Lead for Cisco Systems, Inc. - San Jose, CA - Ricki Martin-Espinoza -X (rickimar - Spherion at Cisco)
[SI-LIST] Flight time compensation - sub mani
[SI-LIST] Simulate IBIS model with transmission line?! - 吳亭瑩
[SI-LIST] Free SerDes modeling toolkit - Todd Westerhoff
[SI-LIST] Re: Flight time compensation - Hargin, Bill
[SI-LIST] Re: Flight time compensation - Todd Westerhoff
[SI-LIST] Re: Flight time compensation - Hargin, Bill
[SI-LIST] Re: Flight time compensation - Todd Westerhoff
[SI-LIST] Re: Help Explaining Microstrip - Ihsan Erdin
[SI-LIST] Re: Help Explaining Microstrip - istvan novak
[SI-LIST] Re: Help Explaining Microstrip - Kihong Joshua Kim
[SI-LIST] Re: Help Explaining Microstrip - Mark Randol
[SI-LIST] Re: Help Explaining Microstrip - SILR
[SI-LIST] Thank you for the SI-LIST - Abe (Abbas) Riazi
[SI-LIST] Re: Thank you for the SI-LIST - Ray Anderson
[SI-LIST] Re: Help Explaining Microstrip - Ihsan Erdin
[SI-LIST] IDE measurement - santhosh.etavalath
[SI-LIST] Result using NEC2++ (2) - Kim Jeong Su
[SI-LIST] DDR2 CMD/CTRL vs. CK Skew compensation problems - LV Fang
[SI-LIST] Re: DDR2 CMD/CTRL vs. CK Skew compensation problems - Jory McKinley
[SI-LIST] Re: Help Explaining Microstrip - Loyer, Jeff
[SI-LIST] Re: Help Explaining Microstrip - Jack Olson
[SI-LIST] Dielectric constant measuring - ma mu
[SI-LIST] Re: Help Explaining Microstrip - Doug Brooks
[SI-LIST] Re: Dielectric constant measuring - Jeon, Tae-Kwang
[SI-LIST] Re: Dielectric constant measuring - Juergen Flamm
[SI-LIST] Fw: Re: Dielectric constant measuring - olaney
[SI-LIST] Re: Help Explaining Microstrip - Mick Zhou
[SI-LIST] Re: Help Explaining Microstrip - Kihong Joshua Kim
[SI-LIST] Re: Help Explaining Microstrip - Asbenson, Lyndell L
[SI-LIST] Re: Help Explaining Microstrip - Russell S. Dudek Jr.
[SI-LIST] Re: Help Explaining Microstrip - Ihsan Erdin
[SI-LIST] Interesting service I saw @ PCB East - steve weir
[SI-LIST] Re: Help Explaining Microstrip - David Instone
[SI-LIST] Re: Help Explaining Microstrip - Paul Levin
[SI-LIST] Re: Help Explaining Microstrip - David Instone
[SI-LIST] Re: Help Explaining Microstrip - olaney
[SI-LIST] Question about VGA termination - Joel Brown
[SI-LIST] Re: Question about VGA termination - olaney
[SI-LIST] Re: Question about VGA termination - Joel Brown
[SI-LIST] Re: Help Explaining Microstrip - Eric Bogatin
[SI-LIST] Re: Help Explaining Microstrip - Peter Csapo
[SI-LIST] laminate-based package - Saoer Sinaga
[SI-LIST] Re: Help Explaining Microstrip - Hal Murray
[SI-LIST] Re: Help Explaining Microstrip - Kihong Joshua Kim
[SI-LIST] DDR2 2-slot design preference... - Jabori, Monji
[SI-LIST] Re: DDR2 2-slot design preference... - steve weir
[SI-LIST] Re: DDR2 2-slot design preference... - Jory McKinley
[SI-LIST] Re: Question about VGA termination - Loyer, Jeff
[SI-LIST] Re: Question about VGA termination - Joel Brown
[SI-LIST] Re: DDR2 2-slot design preference... - Lee Ritchey
[SI-LIST] Re: DDR2 2-slot design preference... - steve weir
[SI-LIST] Re: DDR2 2-slot design preference... - olaney
[SI-LIST] Re: DDR2 2-slot design preference... - steve weir
[SI-LIST] Re: DDR2 2-slot design preference... - Lee Ritchey
[SI-LIST] Re: DDR2 2-slot design preference... - steve weir
[SI-LIST] Re: DDR2 2-slot design preference... - istvan novak
[SI-LIST] Re: DDR2 2-slot design preference... - Scott McMorrow
[SI-LIST] Re: DDR2 2-slot design preference... - Peter Sørensen
[SI-LIST] Re: DDR2 2-slot design preference... - Istvan Novak - Board Design Technology
[SI-LIST] Re: DDR2 2-slot design preference... - pritchard_jason
[SI-LIST] Re: DDR2 2-slot design preference... - Lee Ritchey
[SI-LIST] Re: DDR2 2-slot design preference... - Lee Ritchey
[SI-LIST] Re: DDR2 2-slot design preference... - Chris Cheng
[SI-LIST] Re: DDR2 2-slot design preference... - pritchard_jason
[SI-LIST] Re: DDR2 2-slot design preference... - art_porter
[SI-LIST] Re: DDR2 2-slot design preference... - Eric Bogatin
[SI-LIST] Re: DDR2 2-slot design preference... - olaney
[SI-LIST] Re: DDR2 2-slot design preference... - Chris Cheng
[SI-LIST] Re: DDR2 2-slot design preference... - Loyer, Jeff
[SI-LIST] Re: DDR2 2-slot design preference... - Vinu Arumugham
[SI-LIST] HSpice field-solver syntax for trapezoidal stripline pair - agathon
[SI-LIST] Re: DDR2 2-slot design preference... - Lee Ritchey
[SI-LIST] Re: DDR2 2-slot design preference... - Scott McMorrow
[SI-LIST] Re: DDR2 2-slot design preference... - Scott McMorrow
[SI-LIST] Re: DDR2 2-slot design preference... - Chris Cheng
[SI-LIST] Re: DDR2 2-slot design preference... - Eric Bogatin
[SI-LIST] Re: DDR2 2-slot design preference... - Jory McKinley
[SI-LIST] Re: DDR2 2-slot design preference... - Vinu Arumugham
[SI-LIST] Re: DDR2 2-slot design preference... - Scott McMorrow
[SI-LIST] Re: DDR2 2-slot design preference... - Chris Cheng
[SI-LIST] Re: HSpice field-solver syntax for trapezoidal stripline pair - Tracy Barclay
[SI-LIST] Re: DDR2 2-slot design preference... - Jory McKinley
[SI-LIST] Re: DDR2 2-slot design preference... - Scott McMorrow