FreeLists / si-list / [SI-LIST] IV and VT data mismatch

[<seshadri.kirankumar@xxxxxxxxx>]

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Hi  IBIS Experts,

         =0D

             I have generated an IBIS model for a clock slicer cell
which has Pin1 as input  and Pin2 as output pin (this intended to
function as CLKOUT ) , the IBIS data generated at Pin2  now with the
IBISCHK4 it is issuing all IV and VT data mismatch Errors as I have
listed in attachments. I have following doubts on this Buffer modeling

=0D

1)  Even though   it says that AC (VT) endpoints and DC(IV) endpoints
are same why it is showing a huge percentage of Error ?

=0D

2) As  this Buffer has some delay, when I apply a rising/Falling pulse
train at Pin1  I have observed the Rising transition is happening after
2nd Pulse onwards whereas Output falling happens at first time onwards.

        So in this case if I Extract VT data i.e Rising and Falling for
2nd  Pulse or any other pulse i.e other than 1st pulse  will it be
fine?  Because the Time scale starts from some finite value other than 0
Seconds  in every table.

=0D

Thanks in advance=0D

=0D

Best Regards

Kirna Kumar

=0D

=0D

     =0D





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